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* x86: Use generic global_dataSimon Glass2013-02-04-34/+3
| | | | | | Move x86 over to use generic global_data. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Remove reset_status, relocoff from global_dataSimon Glass2013-02-01-2/+0
| | | | | | These fields are not used on x86, so punt them. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move gd_addr into arch_global_dataSimon Glass2013-02-01-4/+3
| | | | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add arch/x86/cpu/cpu.c changes after Graeme's comments] Signed-off-by: Tom Rini <trini@ti.com>
* x86: Set up the global data pointer in C instead of asmSimon Glass2013-02-01-7/+3
| | | | | | | | | | | | | | | | We currently assume that the global data pointer is at the start of struct global_data. We want to remove this restriction, and it is easiest to do this in C. Remove the asm code and add equivalent code in C. This idea was proposed by Graeme Russ here: http://patchwork.ozlabs.org/patch/199741/ Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Apply Graeme Russ' comments http://patchwork.ozlabs.org/patch/206305/ here, re-order] Signed-off-by: Tom Rini <trini@ti.com>
* x86: Remove gdt_addr from arch_global_dataSimon Glass2013-02-01-1/+0
| | | | | | Remove this unused field. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add architecture-specific global dataSimon Glass2013-02-01-2/+8
| | | | | | | | | | | | | We plan to move architecture-specific data into a separate structure so that we can make the rest of it common. As a first step, create struct arch_global_data to hold these fields. Initially it is empty. This patch applies to all archs at once. I can split it if this is really a pain. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Build vga video code only if CONFIG_VIDEO_VGA is definedSimon Glass2012-12-06-2/+2
| | | | | | | When running from coreboot we don't want this code, so make it optional. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Remove video_init() prototype from u-boot-x86.hSimon Glass2012-12-06-1/+0
| | | | | | | | | This function is not intended to be exported from the video drivers, so remove the prototype. This fixes an error: cfb_console.c:1793:12: error: static declaration of 'video_init' follows non-static declaration Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: drop unused code in coreboot.cStefan Reinauer2012-12-06-7/+0
| | | | | | | | | | | The function setup_pcat_compatibility() is weak and implemented as empty function in board.c hence we don't have to override that with another empty function. monitor_flash_len is unused, drop it. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Remove coreboot_ from file nameStefan Reinauer2012-12-06-2/+1
| | | | | | | ... because that information is already "encoded" in the directory name. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Provide a way to throttle port80 accessesVadim Bendebury2012-12-06-0/+21
| | | | | | | | | | | | | | | | | | | | | | | Some systems (like Google Link device) provide the ability to keep a history of the target CPU port80 accesses, which is extremely handy for debugging. The problem is that the EC handling port 80 access is orders of magnitude slower than the AP. This causes random loss of trace data. This change allows to throttle port 80 accesses such that in case the AP is trying to post faster than the EC can handle, a delay is introduced to make sure that the post rate is throttled. Experiments have shown that on Link the delay should be at least 350,000 of tsc clocks. Throttling is not being enabled by default: to enable it one would have to set MIN_PORT80_KCLOCKS_DELAY to something like 400 and rebuild the u-boot image. With upcoming EC code optimizations this number could be decreased (new new value should be established experimentally). Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Provide tick counter and frequency reference for Intel core architectureVadim Bendebury2012-12-06-0/+31
| | | | | | | | | | | | | | | Some u-boot modules rely on availability of get_ticks() and get_tbclk() functions, reporting a free running clock and its frequency respectively. Traditionally these functions return number and frequency of timer interrupts. Intel's core architecture processors however are known to run the rdtsc instruction at a constant rate of the so called 'Max Non Turbo ratio' times the external clock frequency which is 100MHz. This is just as good for the timer tick functions in question. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Issue SMI to finalize Coreboot in final stageDuncan Laurie2012-12-06-0/+4
| | | | | | | | | This will write magic value to APMC command port which will trigger an SMI and cause coreboot to lock down the ME, chipset, and CPU. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Fix MTRR clear to detect which MTRR to useDuncan Laurie2012-12-06-4/+15
| | | | | | | | | | | | Coreboot was always using MTRR 7 for the write-protect cache entry that covers the ROM and U-boot was removing it. However with 4GB configs we need more MTRRs for the BIOS and so the WP MTRR needs to move. Instead coreboot will always use the last available MTRR that is normally set aside for OS use and U-boot can clear it before the OS. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Emit port 80 post codes in show_boot_progress()Stefan Reinauer2012-12-06-0/+2
| | | | | | | | | This helps us monitor boot progress and determine where U-Boot dies if there are any problems. Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: fdt: Create basic .dtsi file for corebootSimon Glass2012-12-06-0/+29
| | | | | | | | This contains just the minimum information for a coreboot-based board. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Set CONFIG_ARCH_DEVICE_TREE correctlyGabe Black2012-12-06-0/+23
| | | | | | | | We will use coreboot.dtsi as our fdt include file. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add support for CONFIG_OF_CONTROLGabe Black2012-12-06-0/+36
| | | | | | | Allow a device tree to be provided through the standard mechanisms. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add CONFIG_DELAY_ENVIRONMENT to delay environment loadingStefan Reinauer2012-12-06-1/+27
| | | | | | | | | | | | | | | | This option delays loading of the environment until later, so that only the default environment will be available to U-Boot. This can address the security risk of untrusted data being used during boot. When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a run-time way of enabling loadinlg of the environment. Add this to the fdt as /config/delay-environment. Note: This patch depends on http://patchwork.ozlabs.org/patch/194342/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
* x86: Add back cold- and warm-boot flagsGabe Black2012-12-06-1/+18
| | | | | | | | | | | | | These were removed, but actually are useful. Cold means that we started from a reset/power on. Warm means that we started from another U-Boot. We determine whether u-boot on x86 was warm or cold booted (really if it started at the beginning of the text segment or at the ELF entry point). We plumb the result through to the global data structure. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Override calculate_relocation_address to use the e820 mapGabe Black2012-12-06-6/+55
| | | | | | | | | | | | | | Because calculate_relocation_address now uses the e820 map, it will be able to avoid addresses over 32 bits and regions that are at high addresses but not big enough for U-Boot. It also means we can remove the hack which limitted U-Boot's idea of the size of memory to less than 4GB. Also take into account the space needed for the heap and stack, so we avoid picking a very small region those areas might overlap with something it shouldn't. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Make calculate_relocation_address an overridable functionGabe Black2012-12-06-1/+2
| | | | | | | | | Different systems may have different mechanisms for picking a suitable place to relocate U-Boot to. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Make the upper bound on relocated symbols closed instead of openGabe Black2012-12-06-1/+1
| | | | | | This seems to be a bug. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Reorder x86's post relocation memory layoutGabe Black2012-12-06-3/+4
| | | | | | | | | | | | | | | | | | | | | | | This changes the layout in decreasing addresses from: 1. Stack 2. Sections in the image 3. Heap to 1. Sections in the image 2. Heap 3. Stack This allows the stack to grow significantly more since it isn't constrained by the other u-boot areas. More importantly, the generic memory wipe code assumes that the stack is the lowest addressed area used by the main part of u-boot. In the original layout, that means that u-boot tramples all over itself. In the new layout, it works. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Initialise SPI if enabledGabe Black2012-12-06-0/+13
| | | | | | | | If we have SPI support, make sure that we init it. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vic Yang <victoryang@chromium.org>
* x86: Implement arch_phys_memset so that it can wipe memory above 4GBGabe Black2012-12-06-0/+229
| | | | | | | | | | | | | | | | | | | | | | Implement arch_phys_memset so that it can set memory at physical addresses above 4GB using PAE paging. Because there are only 5 page tables in PAE mode, 1 PDPT and 4 PDTs, those tables are statically allocated in the BSS. The tables must be 4K page aligned and are declared that way, and because U-Boot starts as 4K aligned and the relocation code relocates it to a 4K aligned address, the tables work as intended. While paging is turned on, all 4GB are identity mapped except for one 2MB page which is used as the window into high memory. This way, U-Boot will continue to work as expected when running code that expects to access memory freely, but the code can still get at high memory through its window. The window is put at 2MB so that it's 2MB page aligned, low in memory to be out of the way of things U-Boot is likely to care about, and above the lowest 1MB where lots of random things live. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Increase the size of the phys_size_t and phys_addr_t typesGabe Black2012-12-06-4/+6
| | | | | | | | | These types should be 64 bits long to reflect the fact that physical addresses and the size of physical areas of memory are more than 32 bits long. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Fix off-by-one error in do_elf_reloc_fixups()Duncan Laurie2012-12-06-1/+1
| | | | | | | | | | The use of post-increment with a do-while loop results in the loop going one step too far when handling relocation fixups. In about 1/100 cases this would cause it to hang. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Ignore memory >4GB when parsing Coreboot tablesDuncan Laurie2012-12-06-0/+4
| | | | | | | | U-boot is unable to actually use that memory and it can cause problems with relocation if it tries to. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Fix indirect jmp warning in zimage.cSimon Glass2012-12-06-3/+3
| | | | | | | | | | | | | | This fixes the following warning: zimage.c:312: Warning: indirect jmp without `*' Also fixed these warnings to keep checkpatch quiet: warning: arch/x86/lib/zimage.c,311: unnecessary whitespace before a quoted newline warning: arch/x86/lib/zimage.c,312: unnecessary whitespace before a quoted newline warning: arch/x86/lib/zimage.c,313: unnecessary whitespace before a quoted newline Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Clean up MTRR 7 right before jumping to the kernelStefan Reinauer2012-12-06-0/+18
| | | | | | | | This cleans up the rom caching optimization implemented in coreboot (and needed throughout U-Boot runtime). Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Import MSR/MTRR code from LinuxGraeme Russ2012-12-06-0/+913
| | | | | | Imported from Linux 3.1 with a few modifications to suit U-Boot Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Provide a function to clean up just before booting a zimageStefan Reinauer2012-12-06-0/+11
| | | | | | | | This function can be used by boards which want to do some clean-up before booting a zImage. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add basic cache operationsStefan Reinauer2012-12-06-72/+155
| | | | | | | Add functions to enable/disable the data cache. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Fill in the dram info using the e820 map on coreboot/x86Gabe Black2012-12-06-0/+15
| | | | | | | | | | | | | | | This way when that dram "banks" are displayed, there's some useful information there. The number of "banks" we claim to have needs to be adjusted so that it covers the number of RAM e820 regions we expect to have/care about. This needs to be done after "RAM" initialization even though we always run from RAM. The bd pointer in the global data structure doesn't automatically point to anything, and it isn't set up until "RAM" is available since, I assume, it would take too much space in the very constrained pre-RAM environment. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a CBMEM timestamp generated right before the kernel startup.Vadim Bendebury2012-12-06-0/+7
| | | | | | | | | | To maintain the initialization state of the timestamp facility, thesq pointer to the CBMEM section containing the timestamp table should be kept in the .data section (so that it is maintained across u-boot relocation). Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Enable coreboot timestamp facility support in u-boot.Vadim Bendebury2012-12-06-0/+117
| | | | | | | | | | | | | | | | | | | | | This change turns on the code which allows u-boot to add timestamps to the timestamp table created by coreboot. Since u-boot does not use the tsc_t like structure to represent HW counter readings, this structure is being replaced by 64 bit integer. The timestamp_init() function is now initializing the base timer value used by u-boot to calculate the HW counter increments. Timestamp facility is initialized as soon as the timestamp table pointer is found in the coreboot table. The u-boot generated timer events' ID will start at 1000 to clearly separate u-boot events from coreboot events in the timer trace. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add function to read time stamp counterVadim Bendebury2012-12-06-0/+29
| | | | | | | | | | | Put this function in the u-boot-x86.h header file. We could instead create timer.h perhaps. We support setting a base time, and reading the time relative to this base. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: gpio: Add GPIO driver for Intel ICH6 and later.Bill Richardson2012-12-06-0/+27
| | | | | | | | | Implement <asm-generic/gpio.h> functions for Intel ICH6 and later. Only GPIOs 0-31 are handled by this code. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Don't spam POST80 codes with slow IO functionsStefan Reinauer2012-11-30-1/+1
| | | | | | | | | | | | | | This patch prevents u-boot from "spamming" random progress codes on a port 80 "post card". The previous version of this patch just removed the delays in the "slow" IO functions, as they do not need to be slow, however, this patch is less intrusive. It uses another unused port that is often used by BIOSes (and the Linux Kernel) for small delay timing purposes. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Fix typo in pcat_timer.cStefan Reinauer2012-11-30-1/+1
| | | | | | | Fix a small comment typo. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Include types.h explicitly in the i386 version of io.hGabe Black2012-11-30-0/+2
| | | | | | | | | | The i386 version of io.h depends on the phys_addr_t type which is defined in types.h. It wasn't including that explicitly, and was working presumably because the other files including it had already included types.h themselves directly or indirectly. This change fixes that. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a dummy implementation for timer_get_usGabe Black2012-11-30-1/+18
| | | | | | | | The microsecond timer is not currently implemented, but add a dummy implementation for now. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a default implementation for cleanup_before_linux()Gabe Black2012-11-30-0/+6
| | | | | | | | | | | This function provides an opportunity for some last minute cleanup and reconfiguration before control is handed over to Linux. It's possible this may need to do something in the future, but for now it's left empty. It's set up as a weak symbol so it can be overridden if necessary on a case by case basis. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add an fdt pointer to the global data structureGabe Black2012-11-30-0/+1
| | | | | | | | This change adds a pointer to the global data structure in x86 to point to the device tree. This mirrors an identical pointer in ARM. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Allow compiling out realmode/bios codeGabe Black2012-11-30-5/+10
| | | | | | | | We don't want this for coreboot, so provide a way of compiling it out. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Decode additional coreboot sysinfo tagsSimon Glass2012-11-30-29/+188
| | | | | | | | | | | Add support for decoding tags for GPIOs, compile/build info, cbmem and other features. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Drop sysinfo.cStefan Reinauer2012-11-30-40/+8
| | | | | | | | | | sysinfo.c only contains the lib_sysinfo data structure which is used/filled by tables.c. This split was introduced by importing code from libpayload originally, but to keep the code simple, add the single line of actual code to tables.c Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Implement recursively scanning PCI bussesGabe Black2012-11-28-3/+23
| | | | | | | | | | | | | | | | | | | | | | A hook is installed to configure PCI bus bridges as they encountered by u-boot. The hook extracts the secondary bus number from the bridge's config space and then recursively scans that bus. On Coreboot, the PCI bus address space has identity mapping with the physical address space, so declare it as such to ensure that the "pci_map_bar" function used by some PCI drivers is behaving properly. This fixes the EHCI PCI driver initialization on Stumpy. This was tested as follows: Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on bus 1, and empty busses 2 through 5. This matches the bridges reported on bus 0 and the PCI configuration output from coreboot. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Tell u-boot about PCI bus 0 when initializingGabe Black2012-11-28-1/+16
| | | | | | | | | | | | | | | | | U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point. It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
generated by cgit v1.1 at 2024-12-28 15:58:22 +0000