summaryrefslogtreecommitdiff
path: root/arch/x86
Commit message (Expand)AuthorAgeLines
* x86: gpio: add pinctrl support from the device treeGabriel Huau2015-06-04-0/+24
* x86: baytrail: pci region 3 is not always mapped to end of ramAndrew Bradford2015-06-04-1/+1
* x86: qemu: Implement PIRQ routingBin Meng2015-06-04-0/+61
* x86: coreboot: Control I/O port 0xb2 writing via device treeBin Meng2015-06-04-3/+10
* x86: qemu: Create separate i440fx and q35 device treesBin Meng2015-06-04-2/+37
* x86: coreboot: Fix cosmetic issuesBin Meng2015-06-04-25/+3
* x86: kconfig: Make FSP_TEMP_RAM_ADDR depend on HAVE_FSPBin Meng2015-06-04-0/+1
* x86: qemu: Adjust VGA initializationBin Meng2015-06-04-19/+17
* x86: qemu: Enable legacy IDE I/O ports decodeBin Meng2015-06-04-0/+38
* x86: qemu: Turn on legacy segments decodeBin Meng2015-06-04-0/+26
* x86: fsp_support: Correct high mem comment typoAndrew Bradford2015-06-04-1/+1
* x86: Do sanity test on pirq table before writingBin Meng2015-06-04-0/+3
* x86: quark: Implement PIRQ routingBin Meng2015-06-04-15/+123
* x86: Refactor PIRQ routing supportBin Meng2015-06-04-300/+383
* x86: qemu: Add graphics supportBin Meng2015-06-04-1/+23
* x86: Move FRAMEBUFFER_SET_VESA_MODE etc to video KconfigBin Meng2015-06-04-141/+0
* x86: Make QEMU the default vendorBin Meng2015-06-04-1/+1
* x86: Support QEMU x86 targetsBin Meng2015-06-04-1/+259
* x86: Enable multi-core init for Minnowboard MAXSimon Glass2015-04-30-0/+20
* x86: Add a CPU driver for baytrailSimon Glass2015-04-30-6/+227
* x86: Allow CPUs to be set up after relocationSimon Glass2015-04-30-0/+54
* x86: Add functions to set and clear bits on MSRsSimon Glass2015-04-30-0/+28
* x86: Add multi-processor initSimon Glass2015-04-30-7/+934
* x86: Provide access to the IDTSimon Glass2015-04-29-0/+7
* x86: Store the GDT pointer in global_dataSimon Glass2015-04-29-0/+2
* x86: Add an mfence macroSimon Glass2015-04-29-0/+5
* x86: Add defines for fixed MTRRsSimon Glass2015-04-29-0/+14
* x86: Add atomic operationsSimon Glass2015-04-29-0/+115
* x86: Add support for the Simple Firmware Interface (SFI)Simon Glass2015-04-29-0/+311
* x86: Disable -WerrorSimon Glass2015-04-29-1/+1
* x86: Remove unwanted MMC debuggingSimon Glass2015-04-29-1/+0
* x86: fsp: Use reset_cpu()Simon Glass2015-04-29-7/+0
* x86: quark: Use reset_cpu()Simon Glass2015-04-29-1/+1
* x86: ivybridge: Use reset_cpu()Simon Glass2015-04-29-15/+6
* x86: Implement reset_cpu() correctly for modern CPUsSimon Glass2015-04-29-13/+28
* x86: link: Add PCH driver to support SPI FlashSimon Glass2015-04-29-1/+12
* x86: minnowmax: use the correct NOR in the configurationGabriel Huau2015-04-29-1/+1
* x86: Correct the typo in write_tables()Bin Meng2015-04-29-1/+1
* x86: Kconfig: Move DM_SPI & DM_SPI_FLASH to arch/KconfigBin Meng2015-04-29-6/+0
* x86: Kconfig: MARK_GRAPHICS_MEM_WRCOMB cosmeticsBin Meng2015-04-29-4/+4
* x86: Kconfig: Move platform options forwardBin Meng2015-04-29-10/+9
* x86: Kconfig: Divide the target selection to vendor/modelBin Meng2015-04-29-79/+13
* x86: quark: Turn on legacy segments decodeBin Meng2015-04-29-0/+19
* x86: Check PIRQ routing table sanity in the F segmentBin Meng2015-04-29-5/+13
* x86: minnowmax: add GPIO banks in the device treeGabriel Huau2015-04-29-0/+42
* x86: baytrail: fix the GPIOBASE addressGabriel Huau2015-04-29-1/+1
* x86: queensbay: Implement PIRQ routingBin Meng2015-04-29-4/+440
* x86: Support platform PIRQ routingBin Meng2015-04-29-0/+300
* x86: Write configuration tables in last_stage_init()Bin Meng2015-04-29-0/+90
* x86: Add a function to assign IRQ numbers to PCI deviceBin Meng2015-04-29-0/+35
generated by cgit v1.1 at 2024-12-15 12:00:21 +0000