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| * x86: Support use of PCI before relocationSimon Glass2014-11-21-0/+31
| | | | | | | | | | | | | | | | Add support for using PCI before SDRAM is available, using early malloc() and global_data. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Refactor PCI to permit alternate initSimon Glass2014-11-21-15/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | We want access PCI earlier in the init sequence, so refactor the code so that it does not require use of a BSS variable to work. This will allow us to use early malloc() to store information about a PCI hose. Common PCI code moves to arch/x86/cpu/pci.c and a new board_pci_setup_hose() function is provided by boards to set up the (single) hose used by that board. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass2014-11-21-3/+311
| | | | | | | | | | | | | | | | Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Emit post codes in startup code for ChromebooksSimon Glass2014-11-21-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Build a .rom file which can be flashed to an x86 machineSimon Glass2014-11-21-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | On x86 machines U-Boot needs to be added to a large ROM image which is then flashed onto the target board. The ROM has a particular format so it makes sense for U-Boot to build this image automatically. Unfortunately it relies on binary blobs so we cannot require this for the default build as yet. Create a u-boot.rom output file for this purpose. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Add chromebook_link boardSimon Glass2014-11-21-0/+298
| | | | | | | | | | | | | | | | | | | | | | | | This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Allow timer calibration to work on ivybridgeSimon Glass2014-11-21-11/+21
| | | | | | | | | | | | | | | | | | | | Unfortunately MSR_FSB_FREQ is not available on this CPU, and the PIT method seems to take up to 50ms which is much too long. For this CPU we know the frequency, so add another special case for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directoryMasahiro Yamada2014-11-21-6/+6
| | | | | | | | | | | | | | | | | | | | The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile are redundant because the build system descends into the directory only when CONFIG_SYS_COREBOOT is defined. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Replace fill_processor_name() with cpu_get_name()Simon Glass2014-11-21-15/+24
| | | | | | | | | | | | | | | | This implementation has a 'cpu' prefix and returns a pointer to the string, avoiding the need for copying. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Remove unnecessary find_fdt(), prepare_fdt() functionsSimon Glass2014-11-21-29/+0
| | | | | | | | | | | | | | These are no-longer needed so drop them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add processor functions to halt and get stack pointerSimon Glass2014-11-21-0/+19
| | | | | | | | | | | | | | Add a function to get the stack pointer and another to halt the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Fix a warning with gcc 4.4.4Simon Glass2014-11-21-0/+1
| | | | | | | | | | | | | | This warning appears even though it seems that the compiler could work it out. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Save TSC frequency in the global dataBin Meng2014-11-21-0/+5
| | | | | | | | | | | | | | | | Return the saved TSC frequency in get_tbclk_mhz(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * x86: Add quick TSC calibration via PITBin Meng2014-11-21-0/+159
| | | | | | | | | | | | | | | | Use the same way that Linux does for quick TSC calibration via PIT when calibration via MSR fails. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Do TSC MSR calibration only for known/supported CPUsBin Meng2014-11-21-7/+108
| | | | | | | | | | | | | | | | | | | | Using MSR_PLATFORM_INFO (0xCE) to calibrate TSR will cause #GP on processors which do not have this MSR. Instead only doing the MSR calibration for known/supported CPUs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * x86: Do CPU identification in the early phaseBin Meng2014-11-21-47/+398
| | | | | | | | | | | | | | The CPU identification happens in x86_cpu_init_f() and corresponding fields are saved in the global data for later use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Save the BIST value on resetSimon Glass2014-11-21-4/+13
| | | | | | | | | | | | | | | | | | | | The built in self test value is available in register eax on start-up. Save it so that it can be accessed later. Unfortunately we must wait until the global_data is available before we can do this, so there is a little bit of shuffling to keep it around. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Fix up some missing prototypesSimon Glass2014-11-21-8/+14
| | | | | | | | | | | | | | Some functions are missing prototypes. Fix those that are specific to x86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Use the standard arch_cpu_init() functionSimon Glass2014-11-21-7/+6
| | | | | | | | | | | | | | | | Instead of an x86-specific cpu_init_f() function, use the normal U-Boot one for this purpose. Also remove a useless/misleading comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Use the standard dram_init() functionSimon Glass2014-11-21-9/+6
| | | | | | | | | | | | | | | | Instead of having an x86-specific DRAM init function, adjust things so we can use the normal one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Tidy up global descriptor table setupSimon Glass2014-11-21-3/+16
| | | | | | | | | | | | | | | | This code is a little muddled, so tidy it up. Make sure that we put the GDT in the right place and set it up properly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Invalidate TLB as early as possibleSimon Glass2014-11-21-0/+3
| | | | | | | | | | | | | | | | We should invalidate the TLB right at the start to ensure that we don't get false address translations even though paging is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Remove board_init16() call which is not usedSimon Glass2014-11-21-9/+1
| | | | | | | | | | | | | | | | This allows a board to do very early init, but no boards need to do this. We may as well drop this feature. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Remove REALMODE_BASE which is no longer usedSimon Glass2014-11-21-1/+0
| | | | | | | | | | | | | | This was missed when the real mode support was dropped. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directoryMasahiro Yamada2014-11-23-7/+7
| | | | | | | | | | | | | | | | | | | | The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile are redundant because the build system descends into the directory only when CONFIG_SYS_COREBOOT is defined. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | kbuild: Descend into SOC directory from CPU directoryMasahiro Yamada2014-11-23-0/+2
| | | | | | | | | | | | | | | | | | Some CPUs of some architectures have SOC directories. At present, the build system directly descends into SOC directories from the top Makefile, but it should generally descend into each directory from its parent directory. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada2014-11-23-2/+2
|/ | | | | | | | | | | | | | | | | | | | U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
* x86: Correct a few progress message nitsSimon Glass2014-10-28-3/+3
| | | | | | | We should use puts() instead of printf() where possible. Also clarify the setup.bin message. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: bootm: Support booting a 64-bit raw kernelSimon Glass2014-10-28-2/+8
| | | | | | Detect an x86_64 kernel and boot it in 64-bit mode. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move kernel boot function to arch/x86/lib/bootm.cSimon Glass2014-10-28-48/+63
| | | | | | | | The boot_zimage() function is badly named it can also boot a raw kernel. Rename it, and try to avoid pointers for memory addresses as it involves lots of casting. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add support for starting 64-bit kernelSimon Glass2014-10-28-1/+165
| | | | | | | | Add code to jump to a 64-bit Linux kernel. We need to set up a flat page table structure, a new GDT and then go through a few hoops in the right order. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Display basic CPU information on bootSimon Glass2014-10-28-0/+71
| | | | | | Display the type of CPU (x86 or x86_64) when starting up. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Bring in msr-index.h from linux 3.8Simon Glass2014-10-28-2/+106
| | | | | | Update this file to include x86_64 fields. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move paging functions into cpu.cSimon Glass2014-10-28-30/+60
| | | | | | | These functions really don't belong in physmem as they relate to the cpu. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Use correct printf() format string for uintptr_tSimon Glass2014-10-27-1/+2
| | | | | | Use the inttypes header file to provide this. Signed-off-by: Simon Glass <sjg@chromium.org>
* Provide option to avoid defining a custom version of uintptr_t.Gabe Black2014-10-27-0/+5
| | | | | | | | | | | | | | | | | | There's a definition in stdint.h (provided by gcc) which will be more correct if available. Define CONFIG_USE_STDINT to use this feature, or USE_STDINT=1 on the 'make' commmand. This adjusts the settings for x86 and sandbox, with both have 64-bit options. Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Bill Richardson <wfrichar@google.com> Rewritten to be an option, since stdint.h is often available only in glibc. Changed to preserve a clear boundary between stdint and non-stdint Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: Convert coreboot serial to use driver modelSimon Glass2014-10-23-12/+2
| | | | | | | This makes use of the existing device tree node to use driver model for the serial console. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: dts: Add additional info to the serial port nodeSimon Glass2014-10-23-3/+20
| | | | | | | Add more information so that U-Boot can find the address of the serial port. Also fix the reg-shift value. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: Add a gpio header for corebootSimon Glass2014-10-23-0/+16
| | | | | | | | This code doesn't follow the normal approach of having its arch-specific definitions in an arch-specific directory. Add a new arch-specific file and make use of it. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: Support pre-reloc malloc()Simon Glass2014-10-23-0/+7
| | | | | | Add support for this by reserving a block of memory below global_data. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: Zero global data before board_init_f()Simon Glass2014-10-23-0/+6
| | | | | | | | To permit information to be passed from the early U-Boot code to board_init_f() we cannot zero the global_data in board_init_f(). Instead zero it in the start-up code. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: Remove ebp assembler warning in zimage.cSimon Glass2014-10-23-1/+0
| | | | | | | This code generates warnings with recent gcc versions. We really don't need the clobber specification, so just drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* kconfig: move CONFIG_USE_PRIVATE_LIBGCC to KconfigMasahiro Yamada2014-10-23-2/+3
| | | | | | | | | | | | | | | The private libgcc is supported only on ARM, MIPS, PowerPC, SH, x86. Those architectures should "select" HAVE_PRIVATE_LIBGCC and CONFIG_USE_PRIVATE_LIBGCC should depend on it. Currently, this option is enabled on Tegra boards and x86 architecture. Move the definition from header files to Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com>
* x86: set CONFIG_USE_PRIVATE_LIBGCC to yMasahiro Yamada2014-10-23-6/+5
| | | | | | | | | | | | | | | | | | The motivation of this commit is to change CONFIG_USE_PRIVATE_LIBGCC to a boolean macro so we can move it to Kconfig. In the current implementation, there are two forms of syntax for this macro: - CONFIG_USE_PRIVATE_LIBGCC=y - CONFIG_USE_PRIVATE_LIBGCC=path/to/private/libgcc The latter is only used by x86 architecture. With a little bit refactoring, it can be converted to the former. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add device tree information for Chrome OS ECSimon Glass2014-10-22-0/+18
| | | | | | Add the required node describing how to find the EC on link. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Fix GDT limit in start16.SBin Meng2014-10-22-1/+1
| | | | | | | GDT limit should be one less than an integral multiple of eight. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Fix rom version build with CONFIG_X86_RESET_VECTORBin Meng2014-10-22-2/+2
| | | | | | | | | | When building U-Boot with CONFIG_X86_RESET_VECTOR, the linking process misses the resetvec.o and start16.o so it cannot generate the rom version of U-Boot. The arch/x86/cpu/Makefile is updated to pull them into the final linking process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Allow cmdline setup in setup_zimage() to be optionalSimon Glass2014-10-22-9/+12
| | | | | | | If we are passing this using the device tree then we may not want to set this up here. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Rewrite bootm.c to make it similar to ARMSimon Glass2014-10-22-53/+130
| | | | | | | | | | | | | The x86 bootm code is quite special, and geared to zimage. Adjust it to support device tree and make it more like the ARM code, with separate bootm stages and functions for each stage. Create a function announce_and_cleanup() to handle printing the "Starting kernel ..." message and put it in bootm so it is in one place and can be used by any loading code. Also move the board_final_cleanup() function into bootm. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Enable LMB and RAMDISK_HIGH by defaultSimon Glass2014-10-22-0/+3
| | | | | | | These options are used by the image code. To allow us to use the generic code more easily, define these for x86. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-08-24 13:16:06 +0000