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* x86: Clean up the FSP support codesBin Meng2014-12-18-290/+279
* x86: Rename coreboot-serial to x86-serialBin Meng2014-12-18-1/+1
* x86: crownbay: Add SDHCI supportBin Meng2014-12-18-1/+48
* x86: crownbay: Add SPI flash supportBin Meng2014-12-18-1/+40
* x86: Use consistent name XXX_ADDR for binary blob flash addressBin Meng2014-12-18-5/+5
* x86: Add queensbay and crownbay Kconfig filesBin Meng2014-12-18-0/+92
* x86: Enable the queensbay cpu directory buildBin Meng2014-12-18-0/+1
* x86: ich6-gpio: Add Intel Tunnel Creek GPIO supportBin Meng2014-12-18-2/+15
* x86: Convert microcode format to device-tree-onlySimon Glass2014-12-18-7/+11
* x86: Add basic support to queensbay platform and crownbay boardBin Meng2014-12-18-0/+326
* x86: Integrate Tunnel Creek processor microcodeBin Meng2014-12-18-0/+368
* x86: Correct problems in the microcode loadingSimon Glass2014-12-18-10/+15
* x86: ivybridge: Update the microcodeSimon Glass2014-12-18-1374/+1504
* x86: Move microcode updates into a separate directorySimon Glass2014-12-18-2/+2
* x86: move arch-specific asmlinkage to <asm/linkage.h>Masahiro Yamada2014-12-15-1/+11
* x86: Add a simple command to show FSP HOB informationBin Meng2014-12-13-0/+68
* x86: Support Intel FSP initialization path in start.SBin Meng2014-12-13-0/+20
* x86: Add post failure codes for bist and carBin Meng2014-12-13-0/+3
* x86: queensbay: Adapt FSP support codesBin Meng2014-12-13-18/+28
* x86: Initial import from Intel FSP release for Queensbay platformBin Meng2014-12-13-0/+1522
* x86: Add a simple superio driver for SMSC LPC47MBin Meng2014-12-13-0/+90
* x86: Add Intel Crown Bay board dts fileBin Meng2014-12-13-1/+55
* x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng2014-12-13-0/+7
* x86: Clean up asm-offsetsBin Meng2014-12-13-2/+3
* x86: Make ROM_SIZE configurable in KconfigBin Meng2014-12-13-1/+77
* Replace <compiler.h> with <linux/compiler.h>Masahiro Yamada2014-12-08-6/+7
* Kbuild: introduce Makefile in arch/$ARCH/Daniel Schwierzeck2014-12-08-0/+12
* x86: dts: Add video information to the device treeSimon Glass2014-11-25-0/+13
* x86: Add initial video device init for Intel GMASimon Glass2014-11-25-1/+927
* x86: Add support for running option ROMs nativelySimon Glass2014-11-25-0/+946
* x86: Add vesa mode configuration optionsSimon Glass2014-11-25-0/+149
* x86: Add GDT descriptors for option ROMsSimon Glass2014-11-25-22/+18
* x86: ivybridge: Add northbridge init functionsSimon Glass2014-11-25-1/+207
* x86: Drop some msr functions that we don't supportSimon Glass2014-11-25-11/+0
* x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+526
* x86: Add LAPIC setup codeSimon Glass2014-11-25-2/+181
* x86: Drop old CONFIG_INTEL_CORE_ARCH codeSimon Glass2014-11-25-28/+0
* x86: Refactor interrupt_init()Bin Meng2014-11-25-14/+23
* x86: Remove cpu_init_r() for x86Bin Meng2014-11-25-8/+0
* x86: Call cpu_init_interrupts() from interrupt_init()Bin Meng2014-11-25-2/+3
* x86: Add Intel speedstep and turbo mode codeSimon Glass2014-11-25-0/+219
* x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+34
* x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+33
* x86: dts: Add SATA settings for linkSimon Glass2014-11-25-0/+7
* x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+306
* x86: dts: Add LPC settings for linkSimon Glass2014-11-25-0/+8
* x86: dts: Move PCI peripherals into a pci nodeSimon Glass2014-11-25-13/+15
* x86: ivybridge: Add additional LPC initSimon Glass2014-11-25-1/+528
* x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+173
* x86: Add a simple header file for ACPISimon Glass2014-11-25-0/+24
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