summaryrefslogtreecommitdiff
path: root/arch/x86
Commit message (Collapse)AuthorAgeLines
* x86: Enable the queensbay cpu directory buildBin Meng2014-12-18-0/+1
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ich6-gpio: Add Intel Tunnel Creek GPIO supportBin Meng2014-12-18-2/+15
| | | | | | | | | | | | Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Convert microcode format to device-tree-onlySimon Glass2014-12-18-7/+11
| | | | | | | | | | To avoid having two microcode formats, adjust the build system to support obtaining the microcode from the device tree, even in the case where it must be made available before the device tree can be accessed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add basic support to queensbay platform and crownbay boardBin Meng2014-12-18-0/+326
| | | | | | | | | | | Implement minimum required functions for the basic support to queensbay platform and crownbay board. Currently the implementation is to call fsp_init() in the car_init(). We may move that call to cpu_init_f() in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Integrate Tunnel Creek processor microcodeBin Meng2014-12-18-0/+368
| | | | | | | | Integrate the processor microcode version 1.05 for Tunnel Creek, CPUID device 20661h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Correct problems in the microcode loadingSimon Glass2014-12-18-10/+15
| | | | | | | | | | | | | There are several problems in the code. The device tree decode is incorrect in ways that are masked due to a matching bug. Both are fixed. Also microcode_read_rev() should be inline and called before the microcode is written. Note: microcode writing does not work correctly on ivybridge for me. Further work is needed to resolve this. But this patch tidies up the existing code so that will be easier. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Update the microcodeSimon Glass2014-12-18-1374/+1504
| | | | | | | | There are new microcode revisions available. Update them. Also change the format so that the first 48 bytes are not omitted from the device tree data. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move microcode updates into a separate directorySimon Glass2014-12-18-2/+2
| | | | | | | We might end up with a few of these, so put them in their own directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: move arch-specific asmlinkage to <asm/linkage.h>Masahiro Yamada2014-12-15-1/+11
| | | | | | | | | | | | | | | | | | Commit 65dd74a674d6 (x86: ivybridge: Implement SDRAM init) introduced x86-specific asmlinkage into arch/x86/include/asm/config.h. Commit ed0a2fbf14f7 (x86: Add a definition of asmlinkage) added the same macro define again, this time, into include/common.h. (Please do not add arch-specific stuff to include/common.h any more; it is already too cluttered.) The generic asmlinkage is defined in <linux/linkage.h>. If you want to override it with an arch-specific one, the best way is to add it to <asm/linkage.h> like Linux Kernel. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Add a simple command to show FSP HOB informationBin Meng2014-12-13-0/+68
| | | | | | | | | | | | | | FSP builds a series of data structures called the Hand-Off-Blocks (HOBs) as it progresses through initializing the silicon. These data structures conform to the HOB format as described in the Platform Initialization (PI) specification Volume 3 Shared Architectual Elements specification, which is part of the UEFI specification. Create a simple command to parse the HOB list to display the HOB address, type and length in bytes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Support Intel FSP initialization path in start.SBin Meng2014-12-13-0/+20
| | | | | | | | | | | | | | | | | Per Intel FSP architecture specification, FSP provides 3 routines for bootloader to call. The first one is the TempRamInit (aka Cache-As-Ram initialization) and the second one is the FspInit which does the memory bring up (like MRC for other x86 targets) and chipset initialization. Those two routines have to be called before U-Boot jumping to board_init_f in start.S. The FspInit() will return several memory blocks called Hand Off Blocks (HOBs) whose format is described in Platform Initialization (PI) specification (part of the UEFI specication) to the bootloader. Save this HOB address to the U-Boot global data for later use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add post failure codes for bist and carBin Meng2014-12-13-0/+3
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Adapt FSP support codesBin Meng2014-12-13-18/+28
| | | | | | | Use inline assembly codes to call FspNotify() to make sure parameters are passed on the stack as required by the FSP calling convention. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Initial import from Intel FSP release for Queensbay platformBin Meng2014-12-13-0/+1522
| | | | | | | | | | | | | | This is the initial import from Intel FSP release for Queensbay platform (Tunnel Creek processor and Topcliff Platform Controller Hub), which can be downloaded from Intel website. For more details, check http://www.intel.com/fsp. Note: U-Boot coding convention was applied to these codes, so it looks completely different from the original Intel release. Also update FSP support codes license header to use SPDX ID. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a simple superio driver for SMSC LPC47MBin Meng2014-12-13-0/+90
| | | | | | | | | On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add Intel Crown Bay board dts fileBin Meng2014-12-13-1/+55
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng2014-12-13-0/+7
| | | | | | | | | Movie setup_pch_gpios() in the ich6-gpio driver to the board support codes, so that the driver does not need to know any platform specific stuff (ie: include the platform specifc chipset header file). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Clean up asm-offsetsBin Meng2014-12-13-2/+3
| | | | | | | | | Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF which is not referenced anymore. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Make ROM_SIZE configurable in KconfigBin Meng2014-12-13-1/+77
| | | | | | | | | | Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This will not be the case when adding additional board support. Hence we make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the board Kconfig file select the default ROM_SIZE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Replace <compiler.h> with <linux/compiler.h>Masahiro Yamada2014-12-08-6/+7
| | | | | | Including <linux/compiler.h> is enough for general use. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Kbuild: introduce Makefile in arch/$ARCH/Daniel Schwierzeck2014-12-08-0/+12
| | | | | | | | | | | | | | | Introduce a Makefile under arch/$ARCH/ and include it in the top Makefile (similar to Linux kernel). This allows further refactoringi like moving architecture-specific code out of global makefiles, deprecating config variables (CPU, CPUDIR, SOC) or deprecating arch/$ARCH/config.mk. In contrary to Linux kernel, U-Boot defines the ARCH variable by Kconfig, thus the arch Makefile can only included conditionally after the top config.mk. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* x86: dts: Add video information to the device treeSimon Glass2014-11-25-0/+13
| | | | | | This provides panel timing information needed by the video driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add initial video device init for Intel GMASimon Glass2014-11-25-1/+927
| | | | | | | | | Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range of video devices. Add code to set up the hardware on ivybridge. Part of the init happens in native code, part of it happens in a 16-bit option ROM for those nostalgic for the 1970s. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add support for running option ROMs nativelySimon Glass2014-11-25-0/+946
| | | | | | | | On x86 machines we can use an emulator to run option ROMS as with other architectures. But with some additional effort (mostly due to the 16-bit nature of option ROMs) we can run them natively. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add vesa mode configuration optionsSimon Glass2014-11-25-0/+149
| | | | | | Add Kconfig options to allow selection of a vesa mode on x86 machines. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add GDT descriptors for option ROMsSimon Glass2014-11-25-22/+18
| | | | | | | Option ROMs require a few additional descriptors. Add these, and remove the enum since we now have to access several descriptors from assembler. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add northbridge init functionsSimon Glass2014-11-25-1/+207
| | | | | | Add init for the northbridge, another part of the platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Drop some msr functions that we don't supportSimon Glass2014-11-25-11/+0
| | | | | | These are not available in U-Boot as yet, so drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+526
| | | | | | Add the setup code for the CPU so that it can be used at full speed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add LAPIC setup codeSimon Glass2014-11-25-2/+181
| | | | | | | Add code to set up the Local Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop old CONFIG_INTEL_CORE_ARCH codeSimon Glass2014-11-25-28/+0
| | | | | | | This is no-longer used, so drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Refactor interrupt_init()Bin Meng2014-11-25-14/+23
| | | | | | | | | | | Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to i8259_init() and create a new interrupt_init() in arch/x86/cpu/interrupt.c to call i8259_init() followed by a call to cpu_init_interrupts(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Remove cpu_init_r() for x86Bin Meng2014-11-25-8/+0
| | | | | | | | | Since cpu_init_interrupts() was moved out of cpu_init_r(), it is useless to keep cpu_init_r() for x86, thus remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Call cpu_init_interrupts() from interrupt_init()Bin Meng2014-11-25-2/+3
| | | | | | | | | | | | | Currently cpu_init_interrupts() is called from cpu_init_r() to setup the interrupt and exception of the cpu core, but at that time the i8259 has not been initialized to mask all the irqs and remap the master i8259 interrupt vector base, so the whole system is at risk of being interrupted, and if interrupted, wrong interrupt/exception message is shown. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Add Intel speedstep and turbo mode codeSimon Glass2014-11-25-0/+219
| | | | | | | Intel chips have a turbo mode where they can run faster for a short period until they reach thermal limits. Add code to adjust and query this feature. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+34
| | | | | | Add init for XHCI so that high-speed USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+33
| | | | | | Add init for EHCI so that USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: dts: Add SATA settings for linkSimon Glass2014-11-25-0/+7
| | | | | | Add the requires settings to enable SATA on link. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+306
| | | | | | Add code to set up the SATA interfaces on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: dts: Add LPC settings for linkSimon Glass2014-11-25-0/+8
| | | | | | Add some settings required to set up the LPC correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: dts: Move PCI peripherals into a pci nodeSimon Glass2014-11-25-13/+15
| | | | | | | | These peripherals should not be at the top level, since they exist inside the PCI bus. We don't have a full device tree node for pci yet, but we should at least put it at the right level. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add additional LPC initSimon Glass2014-11-25-1/+528
| | | | | | | Set up all the remaining pieces of the LPC (low-pin-count) peripheral in PCH (Peripheral Controller Hub). Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+173
| | | | | | Add required init for the Intel Platform Controller Hub in ivybridge. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a simple header file for ACPISimon Glass2014-11-25-0/+24
| | | | | | | We don't use many features yet, so this only has a few declarations. It will be expanded as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-25-0/+167
| | | | | | Add basic setup for the PCH. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Set up edge triggering on interrupt 9Simon Glass2014-11-25-0/+49
| | | | | | | Add this additional init in case it is needed by the OS. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: pci: Add handlers before and after a PCI hose scanSimon Glass2014-11-25-0/+15
| | | | | | | | Some boards will want to do some setup before and after a PCI hose is scanned. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add ioapic.h headerSimon Glass2014-11-25-0/+38
| | | | | | Add definitions for the I/O Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Factor out common values in the link scriptSimon Glass2014-11-25-7/+12
| | | | | | | | | Define the reset base in config.mk so that it does not need to be calculated twice in the link script. Also tidy up the START_16 and RESET_VEC_LOC values to fit with this new approach. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Ensure that all relocation data is included in the imageSimon Glass2014-11-25-1/+3
| | | | | | | | | Some toolchains put the relocation data into separate sections. Adjust the linker script to catch this case. Without relocation data, U-Boot will not boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-09 16:12:36 +0000