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* x86: Add common SDRAM-init codeSimon Glass2016-03-17-0/+55
* x86: Move common PCH code into a common placeSimon Glass2016-03-17-53/+56
* x86: Add a function to set the IOAPIC IDSimon Glass2016-03-17-0/+2
* x86: broadwell: Add support for SDRAM setupSimon Glass2016-03-17-0/+201
* x86: broadwell: Add power-control supportSimon Glass2016-03-17-0/+129
* x86: broadwell: Add an LPC driverSimon Glass2016-03-17-0/+32
* x86: broadwell: Add a pinctrl driverSimon Glass2016-03-17-0/+91
* x86: broadwell: Add a PCH driverSimon Glass2016-03-17-0/+153
* x86: Add basic support for broadwellSimon Glass2016-03-17-0/+446
* x86: Add support for running Intel reference codeSimon Glass2016-03-17-0/+12
* x86: Drop all the old pin configuration codeSimon Glass2016-03-17-141/+0
* x86: Add an ICH6 pin configuration driverSimon Glass2016-03-17-0/+1
* x86: Update microcode for secondary CPUsSimon Glass2016-03-17-0/+3
* x86: Record the CPU details when starting each coreSimon Glass2016-03-17-0/+9
* x86: Allow I/O functions to use pointersSimon Glass2016-03-17-2/+10
* x86: Add macros to clear and set I/O bitsSimon Glass2016-03-17-0/+22
* x86: ivybridge: Drop sandybridge_early_init()Simon Glass2016-03-17-2/+0
* x86: Move Intel Management Engine code to a common placeSimon Glass2016-03-17-334/+393
* x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass2016-03-17-1/+1
* x86: Move common CPU code to its own placeSimon Glass2016-03-17-2/+44
* x86: Move common LPC code to its own placeSimon Glass2016-03-17-2/+59
* x86: Add the root-complex block to common intel registersSimon Glass2016-03-17-5/+4
* x86: Create a common header for Intel register accessSimon Glass2016-03-17-3/+15
* x86: Move microcode code to a common locationSimon Glass2016-03-17-0/+0
* x86: cpu: Add functions to return the family and steppingSimon Glass2016-03-17-0/+14
* x86: Add comments to the SIPI vectorSimon Glass2016-03-17-0/+1
* x86: Correct duplicate POST valuesSimon Glass2016-03-17-2/+2
* x86: gpio: Correct GPIO setup orderingSimon Glass2016-03-17-0/+5
* x86: Add some more common MSR indexesSimon Glass2016-03-17-18/+40
* x86: Support booting SeaBIOSBin Meng2016-03-17-0/+3
* x86: Implement functions for writing coreboot tableBin Meng2016-03-17-0/+10
* x86: Change write_acpi_tables() signature a little bitBin Meng2016-03-17-1/+1
* x86: Use a macro for ROM table alignmentBin Meng2016-03-17-0/+2
* x86: Clean up coreboot_tables.hBin Meng2016-03-17-73/+80
* x86: Move sysinfo related to sysinfo.hBin Meng2016-03-17-4/+2
* x86: Move asm/arch-coreboot/tables.h to a common placeBin Meng2016-03-17-1/+1
* x86: ivybridge: Add FSP supportBin Meng2016-02-21-0/+52
* x86: Drop pci_type1.c and DEFINE_PCI_DEVICE_TABLEBin Meng2016-02-05-7/+0
* x86: pci: Drop legacy PCI APIsBin Meng2016-02-05-12/+0
* x86: irq: Move irq_router to a per driver privBin Meng2016-02-05-4/+8
* x86: Drop asm/arch/gpio.hBin Meng2016-02-05-89/+0
* x86: qemu: add the ability to load and link ACPI tables from QEMUMiao Yan2016-01-28-0/+61
* x86: qemu: setup PM IO base for ACPI in southbridgeMiao Yan2016-01-28-0/+7
* x86: qemu: re-structure qemu_fwcfg_list_firmware()Miao Yan2016-01-28-3/+6
* x86: baytrail: Add option to disable the internal UART to setup_early_uart()Stefan Roese2016-01-28-1/+1
* x86: ivybridge: Use syscon for the GMA deviceSimon Glass2016-01-24-2/+4
* x86: Set up a shared syscon numbering schemaSimon Glass2016-01-24-0/+9
* x86: ivybridge: Drop XHCI supportSimon Glass2016-01-24-1/+0
* x86: ivybridge: Drop special EHCI initSimon Glass2016-01-24-1/+0
* x86: ivybridge: Sort out the calls to bridge_silicon_revision()Simon Glass2016-01-24-1/+7
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