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* x86: Clean up the FSP support codesBin Meng2014-12-18-134/+140
| | | | | | | | | | | | | | | | | | | | | | | | | This is the follow-on patch to clean up the FSP support codes: - Remove the _t suffix on the structures defines - Use __packed for structure defines - Use U-Boot's assert() - Use standard bool true/false - Remove read_unaligned64() - Use memcmp() in the compare_guid() - Remove the cast in the memset() call - Replace some magic numbers with macros - Use panic() when no valid FSP image header is found - Change some FSP utility routines to use an fsp_ prefix - Add comment blocks for asm_continuation and fsp_init_done - Remove some casts in find_fsp_header() - Change HOB access macros to static inline routines - Add comments to mention find_fsp_header() may be called in a stackless environment - Add comments to mention init(&params) in fsp_init() cannot be removed Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Add SPI flash supportBin Meng2014-12-18-0/+15
| | | | | | | | | The Crown Bay board has an SST25VF016B flash connected to the Tunnel Creek processor SPI controller used as the BIOS media where U-Boot is stored. Enable this flash support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ich6-gpio: Add Intel Tunnel Creek GPIO supportBin Meng2014-12-18-2/+15
| | | | | | | | | | | | Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add basic support to queensbay platform and crownbay boardBin Meng2014-12-18-0/+3
| | | | | | | | | | | Implement minimum required functions for the basic support to queensbay platform and crownbay board. Currently the implementation is to call fsp_init() in the car_init(). We may move that call to cpu_init_f() in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: move arch-specific asmlinkage to <asm/linkage.h>Masahiro Yamada2014-12-15-1/+8
| | | | | | | | | | | | | | | | | | Commit 65dd74a674d6 (x86: ivybridge: Implement SDRAM init) introduced x86-specific asmlinkage into arch/x86/include/asm/config.h. Commit ed0a2fbf14f7 (x86: Add a definition of asmlinkage) added the same macro define again, this time, into include/common.h. (Please do not add arch-specific stuff to include/common.h any more; it is already too cluttered.) The generic asmlinkage is defined in <linux/linkage.h>. If you want to override it with an arch-specific one, the best way is to add it to <asm/linkage.h> like Linux Kernel. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Support Intel FSP initialization path in start.SBin Meng2014-12-13-0/+3
| | | | | | | | | | | | | | | | | Per Intel FSP architecture specification, FSP provides 3 routines for bootloader to call. The first one is the TempRamInit (aka Cache-As-Ram initialization) and the second one is the FspInit which does the memory bring up (like MRC for other x86 targets) and chipset initialization. Those two routines have to be called before U-Boot jumping to board_init_f in start.S. The FspInit() will return several memory blocks called Hand Off Blocks (HOBs) whose format is described in Platform Initialization (PI) specification (part of the UEFI specication) to the bootloader. Save this HOB address to the U-Boot global data for later use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add post failure codes for bist and carBin Meng2014-12-13-0/+2
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Adapt FSP support codesBin Meng2014-12-13-1/+1
| | | | | | | Use inline assembly codes to call FspNotify() to make sure parameters are passed on the stack as required by the FSP calling convention. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Initial import from Intel FSP release for Queensbay platformBin Meng2014-12-13-0/+1096
| | | | | | | | | | | | | | This is the initial import from Intel FSP release for Queensbay platform (Tunnel Creek processor and Topcliff Platform Controller Hub), which can be downloaded from Intel website. For more details, check http://www.intel.com/fsp. Note: U-Boot coding convention was applied to these codes, so it looks completely different from the original Intel release. Also update FSP support codes license header to use SPDX ID. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a simple superio driver for SMSC LPC47MBin Meng2014-12-13-0/+90
| | | | | | | | | On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng2014-12-13-0/+7
| | | | | | | | | Movie setup_pch_gpios() in the ich6-gpio driver to the board support codes, so that the driver does not need to know any platform specific stuff (ie: include the platform specifc chipset header file). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Replace <compiler.h> with <linux/compiler.h>Masahiro Yamada2014-12-08-3/+3
| | | | | | Including <linux/compiler.h> is enough for general use. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* x86: Add initial video device init for Intel GMASimon Glass2014-11-25-0/+2
| | | | | | | | | Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range of video devices. Add code to set up the hardware on ivybridge. Part of the init happens in native code, part of it happens in a 16-bit option ROM for those nostalgic for the 1970s. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add GDT descriptors for option ROMsSimon Glass2014-11-25-19/+12
| | | | | | | Option ROMs require a few additional descriptors. Add these, and remove the enum since we now have to access several descriptors from assembler. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add northbridge init functionsSimon Glass2014-11-25-1/+16
| | | | | | Add init for the northbridge, another part of the platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Drop some msr functions that we don't supportSimon Glass2014-11-25-11/+0
| | | | | | These are not available in U-Boot as yet, so drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+5
| | | | | | Add the setup code for the CPU so that it can be used at full speed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add LAPIC setup codeSimon Glass2014-11-25-2/+123
| | | | | | | Add code to set up the Local Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Refactor interrupt_init()Bin Meng2014-11-25-0/+2
| | | | | | | | | | | Rename interrupt_init() in arch/x86/lib/pcat_interrupts.c to i8259_init() and create a new interrupt_init() in arch/x86/cpu/interrupt.c to call i8259_init() followed by a call to cpu_init_interrupts(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Remove cpu_init_r() for x86Bin Meng2014-11-25-2/+0
| | | | | | | | | Since cpu_init_interrupts() was moved out of cpu_init_r(), it is useless to keep cpu_init_r() for x86, thus remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Add Intel speedstep and turbo mode codeSimon Glass2014-11-25-0/+120
| | | | | | | Intel chips have a turbo mode where they can run faster for a short period until they reach thermal limits. Add code to adjust and query this feature. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+1
| | | | | | Add init for XHCI so that high-speed USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+1
| | | | | | Add init for EHCI so that USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+60
| | | | | | Add code to set up the SATA interfaces on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+49
| | | | | | Add required init for the Intel Platform Controller Hub in ivybridge. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a simple header file for ACPISimon Glass2014-11-25-0/+24
| | | | | | | We don't use many features yet, so this only has a few declarations. It will be expanded as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-25-0/+27
| | | | | | Add basic setup for the PCH. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Set up edge triggering on interrupt 9Simon Glass2014-11-25-0/+11
| | | | | | | Add this additional init in case it is needed by the OS. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: pci: Add handlers before and after a PCI hose scanSimon Glass2014-11-25-0/+3
| | | | | | | | Some boards will want to do some setup before and after a PCI hose is scanned. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add ioapic.h headerSimon Glass2014-11-25-0/+38
| | | | | | Add definitions for the I/O Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Implement SDRAM initSimon Glass2014-11-21-0/+613
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add LAPIC supportSimon Glass2014-11-21-0/+160
| | | | | | | | The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add support for early GPIO initSimon Glass2014-11-21-6/+158
| | | | | | | | | | | | | | When not relying on Coreboot for GPIO init the GPIOs must be set up correctly. This is currently done statically through a rather ugly method. As the GPIOs are figured out they can be moved to the device tree and set up as needed rather than all at the start. In this implementation, board files should call ich_gpio_set_gpio_map() before the GPIO driver is used in order to provide the GPIO information. We use the early PCI interface so that this driver can now be used before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add early init for PCH devicesSimon Glass2014-11-21-1/+237
| | | | | | | Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Perform Intel microcode update on bootSimon Glass2014-11-21-0/+20
| | | | | | | Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Perform initial CPU setupSimon Glass2014-11-21-0/+144
| | | | | | | Set up the flex ratio (controls speed versus heat output) and a few other very early things. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add msr read/write functions that use a structureSimon Glass2014-11-21-0/+19
| | | | | | | | It is convenient to be able to adjust MSRs with a structure that splits the two 32-bit halves into separate fields, as they are often dealt with separately. Add a few functions to support this. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add clr/setbits functionsSimon Glass2014-11-21-0/+49
| | | | | | These are available on other architectures. Make them available on x86 also. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add early LPC init so that serial worksSimon Glass2014-11-21-0/+48
| | | | | | | | The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: pci: Allow configuration before relocationSimon Glass2014-11-21-0/+13
| | | | | | | | | | Add simple PCI access routines for x86 which permit use before relocation. The normal PCI stack is still used, but for pre-relocation use there can only ever be a single hose. After relocation, fall back to the normal access, although even then on x86 machines there is normally only a single PCI bus. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Support use of PCI before relocationSimon Glass2014-11-21-0/+10
| | | | | | | | Add support for using PCI before SDRAM is available, using early malloc() and global_data. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Refactor PCI to permit alternate initSimon Glass2014-11-21-0/+11
| | | | | | | | | | | | | We want access PCI earlier in the init sequence, so refactor the code so that it does not require use of a BSS variable to work. This will allow us to use early malloc() to store information about a PCI hose. Common PCI code moves to arch/x86/cpu/pci.c and a new board_pci_setup_hose() function is provided by boards to set up the (single) hose used by that board. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass2014-11-21-1/+133
| | | | | | | | Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Emit post codes in startup code for ChromebooksSimon Glass2014-11-21-0/+32
| | | | | | | | | | | | | | | | On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add chromebook_link boardSimon Glass2014-11-21-0/+10
| | | | | | | | | | | | This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Replace fill_processor_name() with cpu_get_name()Simon Glass2014-11-21-3/+9
| | | | | | | | This implementation has a 'cpu' prefix and returns a pointer to the string, avoiding the need for copying. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove unnecessary find_fdt(), prepare_fdt() functionsSimon Glass2014-11-21-2/+0
| | | | | | | These are no-longer needed so drop them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add processor functions to halt and get stack pointerSimon Glass2014-11-21-0/+19
| | | | | | | Add a function to get the stack pointer and another to halt the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Save TSC frequency in the global dataBin Meng2014-11-21-0/+1
| | | | | | | | Return the saved TSC frequency in get_tbclk_mhz(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Add quick TSC calibration via PITBin Meng2014-11-21-0/+3
| | | | | | | | Use the same way that Linux does for quick TSC calibration via PIT when calibration via MSR fails. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-09 20:55:18 +0000