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* x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+1
* x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+1
* x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+60
* x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+49
* x86: Add a simple header file for ACPISimon Glass2014-11-25-0/+24
* x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-25-0/+27
* x86: Set up edge triggering on interrupt 9Simon Glass2014-11-25-0/+11
* x86: pci: Add handlers before and after a PCI hose scanSimon Glass2014-11-25-0/+3
* x86: Add ioapic.h headerSimon Glass2014-11-25-0/+38
* x86: ivybridge: Implement SDRAM initSimon Glass2014-11-21-0/+613
* x86: ivybridge: Add LAPIC supportSimon Glass2014-11-21-0/+160
* x86: ivybridge: Add support for early GPIO initSimon Glass2014-11-21-6/+158
* x86: ivybridge: Add early init for PCH devicesSimon Glass2014-11-21-1/+237
* x86: ivybridge: Perform Intel microcode update on bootSimon Glass2014-11-21-0/+20
* x86: ivybridge: Perform initial CPU setupSimon Glass2014-11-21-0/+144
* x86: Add msr read/write functions that use a structureSimon Glass2014-11-21-0/+19
* x86: Add clr/setbits functionsSimon Glass2014-11-21-0/+49
* x86: ivybridge: Add early LPC init so that serial worksSimon Glass2014-11-21-0/+48
* x86: pci: Allow configuration before relocationSimon Glass2014-11-21-0/+13
* x86: Support use of PCI before relocationSimon Glass2014-11-21-0/+10
* x86: Refactor PCI to permit alternate initSimon Glass2014-11-21-0/+11
* x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass2014-11-21-1/+133
* x86: Emit post codes in startup code for ChromebooksSimon Glass2014-11-21-0/+32
* x86: Add chromebook_link boardSimon Glass2014-11-21-0/+10
* x86: Replace fill_processor_name() with cpu_get_name()Simon Glass2014-11-21-3/+9
* x86: Remove unnecessary find_fdt(), prepare_fdt() functionsSimon Glass2014-11-21-2/+0
* x86: Add processor functions to halt and get stack pointerSimon Glass2014-11-21-0/+19
* x86: Save TSC frequency in the global dataBin Meng2014-11-21-0/+1
* x86: Add quick TSC calibration via PITBin Meng2014-11-21-0/+3
* x86: Do CPU identification in the early phaseBin Meng2014-11-21-4/+169
* x86: Save the BIST value on resetSimon Glass2014-11-21-0/+1
* x86: Fix up some missing prototypesSimon Glass2014-11-21-0/+9
* x86: Use the standard arch_cpu_init() functionSimon Glass2014-11-21-0/+1
* x86: Use the standard dram_init() functionSimon Glass2014-11-21-2/+2
* x86: Move kernel boot function to arch/x86/lib/bootm.cSimon Glass2014-10-28-3/+17
* x86: Add support for starting 64-bit kernelSimon Glass2014-10-28-0/+26
* x86: Display basic CPU information on bootSimon Glass2014-10-28-0/+7
* x86: Bring in msr-index.h from linux 3.8Simon Glass2014-10-28-2/+106
* x86: Move paging functions into cpu.cSimon Glass2014-10-28-0/+22
* Provide option to avoid defining a custom version of uintptr_t.Gabe Black2014-10-27-0/+5
* dm: x86: Convert coreboot serial to use driver modelSimon Glass2014-10-23-10/+0
* dm: x86: Add a gpio header for corebootSimon Glass2014-10-23-0/+16
* kconfig: move CONFIG_USE_PRIVATE_LIBGCC to KconfigMasahiro Yamada2014-10-23-2/+0
* x86: set CONFIG_USE_PRIVATE_LIBGCC to yMasahiro Yamada2014-10-23-0/+2
* x86: Rewrite bootm.c to make it similar to ARMSimon Glass2014-10-22-0/+12
* x86: Enable LMB and RAMDISK_HIGH by defaultSimon Glass2014-10-22-0/+3
* x86: delete unused header filesMasahiro Yamada2014-01-24-193/+0
* cosmetic: remove empty lines at the top of fileMasahiro Yamada2013-11-08-1/+0
* SPDX-License-Identifier: convert BSD-3-Clause filesWolfgang Denk2013-08-19-44/+2
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-337/+21
generated by cgit v1.1 at 2024-11-13 04:22:33 +0000