summaryrefslogtreecommitdiff
path: root/arch/x86/include/asm
Commit message (Collapse)AuthorAgeLines
...
* x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+49
| | | | | | Add required init for the Intel Platform Controller Hub in ivybridge. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a simple header file for ACPISimon Glass2014-11-25-0/+24
| | | | | | | We don't use many features yet, so this only has a few declarations. It will be expanded as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-25-0/+27
| | | | | | Add basic setup for the PCH. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Set up edge triggering on interrupt 9Simon Glass2014-11-25-0/+11
| | | | | | | Add this additional init in case it is needed by the OS. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: pci: Add handlers before and after a PCI hose scanSimon Glass2014-11-25-0/+3
| | | | | | | | Some boards will want to do some setup before and after a PCI hose is scanned. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add ioapic.h headerSimon Glass2014-11-25-0/+38
| | | | | | Add definitions for the I/O Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Implement SDRAM initSimon Glass2014-11-21-0/+613
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add LAPIC supportSimon Glass2014-11-21-0/+160
| | | | | | | | The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add support for early GPIO initSimon Glass2014-11-21-6/+158
| | | | | | | | | | | | | | When not relying on Coreboot for GPIO init the GPIOs must be set up correctly. This is currently done statically through a rather ugly method. As the GPIOs are figured out they can be moved to the device tree and set up as needed rather than all at the start. In this implementation, board files should call ich_gpio_set_gpio_map() before the GPIO driver is used in order to provide the GPIO information. We use the early PCI interface so that this driver can now be used before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add early init for PCH devicesSimon Glass2014-11-21-1/+237
| | | | | | | Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Perform Intel microcode update on bootSimon Glass2014-11-21-0/+20
| | | | | | | Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Perform initial CPU setupSimon Glass2014-11-21-0/+144
| | | | | | | Set up the flex ratio (controls speed versus heat output) and a few other very early things. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add msr read/write functions that use a structureSimon Glass2014-11-21-0/+19
| | | | | | | | It is convenient to be able to adjust MSRs with a structure that splits the two 32-bit halves into separate fields, as they are often dealt with separately. Add a few functions to support this. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add clr/setbits functionsSimon Glass2014-11-21-0/+49
| | | | | | These are available on other architectures. Make them available on x86 also. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add early LPC init so that serial worksSimon Glass2014-11-21-0/+48
| | | | | | | | The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: pci: Allow configuration before relocationSimon Glass2014-11-21-0/+13
| | | | | | | | | | Add simple PCI access routines for x86 which permit use before relocation. The normal PCI stack is still used, but for pre-relocation use there can only ever be a single hose. After relocation, fall back to the normal access, although even then on x86 machines there is normally only a single PCI bus. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Support use of PCI before relocationSimon Glass2014-11-21-0/+10
| | | | | | | | Add support for using PCI before SDRAM is available, using early malloc() and global_data. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Refactor PCI to permit alternate initSimon Glass2014-11-21-0/+11
| | | | | | | | | | | | | We want access PCI earlier in the init sequence, so refactor the code so that it does not require use of a BSS variable to work. This will allow us to use early malloc() to store information about a PCI hose. Common PCI code moves to arch/x86/cpu/pci.c and a new board_pci_setup_hose() function is provided by boards to set up the (single) hose used by that board. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass2014-11-21-1/+133
| | | | | | | | Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Emit post codes in startup code for ChromebooksSimon Glass2014-11-21-0/+32
| | | | | | | | | | | | | | | | On x86 it is common to use 'post codes' which are 8-bit hex values emitted from the code and visible to the user. Traditionally two 7-segment displays were made available on the motherboard to show the last post code that was emitted. This allows diagnosis of a boot problem since it is possible to see where the code got to before it died. On modern hardware these codes are not normally visible. On Chromebooks they are displayed by the Embedded Controller (EC), so it is useful to emit them. We must enable this feature for the EC to see the codes, so add an option for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add chromebook_link boardSimon Glass2014-11-21-0/+10
| | | | | | | | | | | | This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Replace fill_processor_name() with cpu_get_name()Simon Glass2014-11-21-3/+9
| | | | | | | | This implementation has a 'cpu' prefix and returns a pointer to the string, avoiding the need for copying. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove unnecessary find_fdt(), prepare_fdt() functionsSimon Glass2014-11-21-2/+0
| | | | | | | These are no-longer needed so drop them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add processor functions to halt and get stack pointerSimon Glass2014-11-21-0/+19
| | | | | | | Add a function to get the stack pointer and another to halt the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Save TSC frequency in the global dataBin Meng2014-11-21-0/+1
| | | | | | | | Return the saved TSC frequency in get_tbclk_mhz(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Add quick TSC calibration via PITBin Meng2014-11-21-0/+3
| | | | | | | | Use the same way that Linux does for quick TSC calibration via PIT when calibration via MSR fails. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Do CPU identification in the early phaseBin Meng2014-11-21-4/+169
| | | | | | | The CPU identification happens in x86_cpu_init_f() and corresponding fields are saved in the global data for later use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Save the BIST value on resetSimon Glass2014-11-21-0/+1
| | | | | | | | | | The built in self test value is available in register eax on start-up. Save it so that it can be accessed later. Unfortunately we must wait until the global_data is available before we can do this, so there is a little bit of shuffling to keep it around. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Fix up some missing prototypesSimon Glass2014-11-21-0/+9
| | | | | | | Some functions are missing prototypes. Fix those that are specific to x86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use the standard arch_cpu_init() functionSimon Glass2014-11-21-0/+1
| | | | | | | | Instead of an x86-specific cpu_init_f() function, use the normal U-Boot one for this purpose. Also remove a useless/misleading comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use the standard dram_init() functionSimon Glass2014-11-21-2/+2
| | | | | | | | Instead of having an x86-specific DRAM init function, adjust things so we can use the normal one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move kernel boot function to arch/x86/lib/bootm.cSimon Glass2014-10-28-3/+17
| | | | | | | | The boot_zimage() function is badly named it can also boot a raw kernel. Rename it, and try to avoid pointers for memory addresses as it involves lots of casting. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add support for starting 64-bit kernelSimon Glass2014-10-28-0/+26
| | | | | | | | Add code to jump to a 64-bit Linux kernel. We need to set up a flat page table structure, a new GDT and then go through a few hoops in the right order. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Display basic CPU information on bootSimon Glass2014-10-28-0/+7
| | | | | | Display the type of CPU (x86 or x86_64) when starting up. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Bring in msr-index.h from linux 3.8Simon Glass2014-10-28-2/+106
| | | | | | Update this file to include x86_64 fields. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move paging functions into cpu.cSimon Glass2014-10-28-0/+22
| | | | | | | These functions really don't belong in physmem as they relate to the cpu. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
* Provide option to avoid defining a custom version of uintptr_t.Gabe Black2014-10-27-0/+5
| | | | | | | | | | | | | | | | | | There's a definition in stdint.h (provided by gcc) which will be more correct if available. Define CONFIG_USE_STDINT to use this feature, or USE_STDINT=1 on the 'make' commmand. This adjusts the settings for x86 and sandbox, with both have 64-bit options. Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Bill Richardson <wfrichar@google.com> Rewritten to be an option, since stdint.h is often available only in glibc. Changed to preserve a clear boundary between stdint and non-stdint Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: Convert coreboot serial to use driver modelSimon Glass2014-10-23-10/+0
| | | | | | | This makes use of the existing device tree node to use driver model for the serial console. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: Add a gpio header for corebootSimon Glass2014-10-23-0/+16
| | | | | | | | This code doesn't follow the normal approach of having its arch-specific definitions in an arch-specific directory. Add a new arch-specific file and make use of it. Signed-off-by: Simon Glass <sjg@chromium.org>
* kconfig: move CONFIG_USE_PRIVATE_LIBGCC to KconfigMasahiro Yamada2014-10-23-2/+0
| | | | | | | | | | | | | | | The private libgcc is supported only on ARM, MIPS, PowerPC, SH, x86. Those architectures should "select" HAVE_PRIVATE_LIBGCC and CONFIG_USE_PRIVATE_LIBGCC should depend on it. Currently, this option is enabled on Tegra boards and x86 architecture. Move the definition from header files to Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com>
* x86: set CONFIG_USE_PRIVATE_LIBGCC to yMasahiro Yamada2014-10-23-0/+2
| | | | | | | | | | | | | | | | | | The motivation of this commit is to change CONFIG_USE_PRIVATE_LIBGCC to a boolean macro so we can move it to Kconfig. In the current implementation, there are two forms of syntax for this macro: - CONFIG_USE_PRIVATE_LIBGCC=y - CONFIG_USE_PRIVATE_LIBGCC=path/to/private/libgcc The latter is only used by x86 architecture. With a little bit refactoring, it can be converted to the former. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Rewrite bootm.c to make it similar to ARMSimon Glass2014-10-22-0/+12
| | | | | | | | | | | | | The x86 bootm code is quite special, and geared to zimage. Adjust it to support device tree and make it more like the ARM code, with separate bootm stages and functions for each stage. Create a function announce_and_cleanup() to handle printing the "Starting kernel ..." message and put it in bootm so it is in one place and can be used by any loading code. Also move the board_final_cleanup() function into bootm. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Enable LMB and RAMDISK_HIGH by defaultSimon Glass2014-10-22-0/+3
| | | | | | | These options are used by the image code. To allow us to use the generic code more easily, define these for x86. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: delete unused header filesMasahiro Yamada2014-01-24-193/+0
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* cosmetic: remove empty lines at the top of fileMasahiro Yamada2013-11-08-1/+0
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* SPDX-License-Identifier: convert BSD-3-Clause filesWolfgang Denk2013-08-19-44/+2
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini Don't remove some copyrights by accident] Signed-off-by: Tom Rini <trini@ti.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-337/+21
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* x86: Support tracing functionSimon Glass2013-06-26-3/+4
| | | | | | | Some changes are needed to x86 timer functions to support tracing. Add these so that the feature works correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Support adding coreboot timestanps to bootstageSimon Glass2013-05-13-0/+7
| | | | | | | Coreboot provides a lot of useful timing information. Provide a facility to add this to bootstage on start-up. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Re-enable PCAT timer 2 for beepingSimon Glass2013-05-13-0/+1
| | | | | | | | While we don't want PCAT timers for timing, we want timer 2 so that we can still make a beep. Re-purpose the PCAT driver for this, and enable it in coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-10-21 09:29:29 +0000