summaryrefslogtreecommitdiff
path: root/arch/x86/include/asm
Commit message (Expand)AuthorAgeLines
* x86: Move common FSP code into a common locationSimon Glass2015-02-05-1/+1
* x86: Rename MMCONF_BASE_ADDRESS and make it common across x86Simon Glass2015-02-05-1/+1
* x86: Implement a cache for Memory Reference Code parametersSimon Glass2015-01-24-0/+54
* x86: Use ipchecksum from net/Simon Glass2015-01-24-37/+0
* x86: Test mtrr support flag before accessing mtrr msrBin Meng2015-01-23-1/+4
* x86: Save mtrr support flag in global dataBin Meng2015-01-23-6/+7
* x86: Support ROMs on other archsSimon Glass2015-01-23-0/+2
* x86: fsp: Drop get_hob_type() and get_hob_length()Bin Meng2015-01-13-34/+4
* x86: ivybridge: Update microcode early in bootSimon Glass2015-01-13-0/+6
* x86: Add support for MTRRsSimon Glass2015-01-13-83/+89
* x86: Drop RAMTOP KconfigSimon Glass2015-01-13-8/+0
* x86: Simplify the fsp hob access functionsBin Meng2015-01-12-30/+21
* pci: Make pci apis usable before relocationBin Meng2015-01-12-2/+1
* x86: Clean up the FSP support codesBin Meng2014-12-18-134/+140
* x86: crownbay: Add SPI flash supportBin Meng2014-12-18-0/+15
* x86: ich6-gpio: Add Intel Tunnel Creek GPIO supportBin Meng2014-12-18-2/+15
* x86: Add basic support to queensbay platform and crownbay boardBin Meng2014-12-18-0/+3
* x86: move arch-specific asmlinkage to <asm/linkage.h>Masahiro Yamada2014-12-15-1/+8
* x86: Support Intel FSP initialization path in start.SBin Meng2014-12-13-0/+3
* x86: Add post failure codes for bist and carBin Meng2014-12-13-0/+2
* x86: queensbay: Adapt FSP support codesBin Meng2014-12-13-1/+1
* x86: Initial import from Intel FSP release for Queensbay platformBin Meng2014-12-13-0/+1096
* x86: Add a simple superio driver for SMSC LPC47MBin Meng2014-12-13-0/+90
* x86: ich6-gpio: Move setup_pch_gpios() to board support codesBin Meng2014-12-13-0/+7
* Replace <compiler.h> with <linux/compiler.h>Masahiro Yamada2014-12-08-3/+3
* x86: Add initial video device init for Intel GMASimon Glass2014-11-25-0/+2
* x86: Add GDT descriptors for option ROMsSimon Glass2014-11-25-19/+12
* x86: ivybridge: Add northbridge init functionsSimon Glass2014-11-25-1/+16
* x86: Drop some msr functions that we don't supportSimon Glass2014-11-25-11/+0
* x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+5
* x86: Add LAPIC setup codeSimon Glass2014-11-25-2/+123
* x86: Refactor interrupt_init()Bin Meng2014-11-25-0/+2
* x86: Remove cpu_init_r() for x86Bin Meng2014-11-25-2/+0
* x86: Add Intel speedstep and turbo mode codeSimon Glass2014-11-25-0/+120
* x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+1
* x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+1
* x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+60
* x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+49
* x86: Add a simple header file for ACPISimon Glass2014-11-25-0/+24
* x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-25-0/+27
* x86: Set up edge triggering on interrupt 9Simon Glass2014-11-25-0/+11
* x86: pci: Add handlers before and after a PCI hose scanSimon Glass2014-11-25-0/+3
* x86: Add ioapic.h headerSimon Glass2014-11-25-0/+38
* x86: ivybridge: Implement SDRAM initSimon Glass2014-11-21-0/+613
* x86: ivybridge: Add LAPIC supportSimon Glass2014-11-21-0/+160
* x86: ivybridge: Add support for early GPIO initSimon Glass2014-11-21-6/+158
* x86: ivybridge: Add early init for PCH devicesSimon Glass2014-11-21-1/+237
* x86: ivybridge: Perform Intel microcode update on bootSimon Glass2014-11-21-0/+20
* x86: ivybridge: Perform initial CPU setupSimon Glass2014-11-21-0/+144
* x86: Add msr read/write functions that use a structureSimon Glass2014-11-21-0/+19
generated by cgit v1.1 at 2024-12-26 08:09:26 +0000