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* x86: Use latest microcode for all BayTrail boardsBin Meng2016-05-23-6568/+0
| | | | | | | | | Update board device tree to include latest microcode, and remove the old no longer needed microcode. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
* x86: baytrail: Update to latest microcodeBin Meng2016-05-23-0/+6568
| | | | | | | | Update BayTrail microcde to rev 325 (for CPUID 30673), rev 907 (for CPUID 30679). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: broadwell: Add a few microcode filesSimon Glass2016-03-17-0/+2272
| | | | | | | Add two microcode files for broadwell. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Add microcode blobs for all the steppingsBin Meng2016-01-13-0/+2472
| | | | | | | | | | | This adds microcode blobs created from Intel FSP package for the Chief River platform. They are for all the Ivy Bridge steppings: 306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the 306a9 which is already in the U-Boot tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Add microcode for BayTrail-I D0 steppingBin Meng2015-08-26-0/+3284
| | | | | | | | This commit adds the microcode blob for BayTrail-I D0 stepping, CPUID signature 30679h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add microcode for BayTrail-I B0 steppingBin Meng2015-08-05-0/+4244
| | | | | | | | This commit adds the microcode blob for BayTrail-I B0 stepping, CPUID signature 30671h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add support for Intel Minnowboard MaxSimon Glass2015-02-06-0/+3284
| | | | | | | | | | | | | | This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Integrate Tunnel Creek processor microcodeBin Meng2014-12-18-0/+368
| | | | | | | | Integrate the processor microcode version 1.05 for Tunnel Creek, CPUID device 20661h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Update the microcodeSimon Glass2014-12-18-1372/+1500
| | | | | | | | There are new microcode revisions available. Update them. Also change the format so that the first 48 bytes are not omitted from the device tree data. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move microcode updates into a separate directorySimon Glass2014-12-18-0/+1372
We might end up with a few of these, so put them in their own directory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>