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* x86: ivybridge: Fix types for 64-bit compilationSimon Glass2017-02-06-2/+2
| | | | | | | Fix a few types that causes warnings on 64-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Add more debugging for failuresSimon Glass2017-02-06-10/+31
| | | | | | | | Add various debug() messages in places where errors occur. This aids with debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Declare global data where it is usedSimon Glass2017-02-06-0/+8
| | | | | | | | Some files are missing this declaration. Add it to avoid build errors when we actually need the declaration. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use unsigned long for address in table generationSimon Glass2017-02-06-1/+1
| | | | | | | | We should use unsigned long rather than u32 for addresses. Update this so that the table-generation code builds correctly on 64-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move efi .lds files into the 'lib' directorySimon Glass2016-11-14-177/+0
| | | | | | | | These files now need to be in a standard place so that they can be located by generic Makefile rules. Move them to the 'lib' directory. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
* Merge tag 'signed-efi-next' of git://github.com/agraf/u-bootTom Rini2016-10-19-1/+56
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch queue for efi - 2016-10-19 Highlights this time around: - Add run time service (power control) support for PSCI (fixed in v3) - Add efi gop pointer exposure - SMBIOS support for EFI (on ARM) - efi pool memory unmap support (needed for 4.8) - initial x86 efi payload support (fixed up in v2) - various bug fixes Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/tables_csum.h
| * x86: efi: Add EFI loader support for x86Simon Glass2016-10-19-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the required pieces to support the EFI loader on x86. Since U-Boot only builds for 32-bit on x86, only a 32-bit EFI application is supported. If a 64-bit kernel must be booted, U-Boot supports this directly using FIT (see doc/uImage.FIT/kernel.its). U-Boot can act as a payload for both 32-bit and 64-bit EFI. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * cpu: Add get_vendor callbackAlexander Graf2016-10-19-0/+16
| | | | | | | | | | | | | | | | | | | | The CPU udevice already has a few callbacks to retreive information about the currently running CPUs. This patch adds a new get_vendor() call that returns the vendor of the main CPUs. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * cpu: Add DMTF id and family fieldsAlexander Graf2016-10-19-0/+5
| | | | | | | | | | | | | | | | | | | | For SMBIOS tables we need to know the CPU family as well as CPU IDs. This patches allocates some space for them in the cpu device and populates it on x86. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Add implementations of setjmp() and longjmp()Simon Glass2016-10-18-1/+62
|/ | | | | | | | Bring in these functions from Linux v4.4. They will be needed for EFI loader support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* libfdt: Bring in upstream stringlist functionsSimon Glass2016-10-13-2/+3
| | | | | | | | | | | | | | These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Convert to use DM coreboot video driverBin Meng2016-10-12-4/+0
| | | | | | | This converts coreboot to use DM framebuffer driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Tidy up enable_clock_gating() for 64-bitSimon Glass2016-10-11-4/+4
| | | | | | | | Fix the hex case and remove unused brackets. Use ~0U instead of ~0UL to allow compilation on 64-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Fix PCH power setupSimon Glass2016-10-11-4/+4
| | | | | | | | At present pch_power_options() has the arguments to writel() around the wrong way. Fix this and update it to compile on 64-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Correct address casts in interrupt codeSimon Glass2016-10-11-2/+2
| | | | | | | We should cast an address to unsigned long, not u32. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Correct address casts in cpu codeSimon Glass2016-10-11-6/+4
| | | | | | | We should cast an address to unsigned long, not u32. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow interrupts to be disabled in 64-bit modeSimon Glass2016-10-11-1/+4
| | | | | | | Update the code to support both 32-bit and 64-bit modes. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: Move link to use driver model for videoSimon Glass2016-10-11-1022/+0
| | | | | | | | Update the configuration to use the new driver. Drop the existing plumbing code and unused header files. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: Move samus to use new driver model supportSimon Glass2016-10-11-1/+0
| | | | | | | Update the samus driver to avoid the direct call to the video BIOS setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: baytrail: Add 2nd eMMC controller to the PCI probe listStefan Roese2016-10-11-2/+3
| | | | | | | | | | With this addition, the eMMC device available on the congatec and DFI BayTrail SoM is detected correctly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: squash lines for immediate returnMasahiro Yamada2016-09-23-28/+4
| | | | | | | | arch_cpu_init() can be simpler by this refactoring. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Add debugging when cpu_common_init() failsSimon Glass2016-08-30-1/+3
| | | | | | | Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Allow microcode to be collatedSimon Glass2016-08-30-1/+11
| | | | | | | | | | | Generally the microcode is combined into a single block only (and removed from the device tree) when there are multiple blocks. But this is not a requirement. Adjust the ivybridge code to avoid assuming this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add debugging when a microcode update failsSimon Glass2016-08-30-1/+3
| | | | | | | | Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher<hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: baytrail: Add SIO HS-UART clock setupStefan Roese2016-08-16-0/+48
| | | | | | | | | | To support the BayTrail internal SIO HS UART, the internal UART clock needs to get configured. This patch adds support for this clock configuration which will be done, if the PCI device(s) are found. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-07-12-0/+49
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| * x86: link: Correct a failure in DRAM initSimon Glass2016-07-12-0/+5
| | | | | | | | | | | | | | | | | | | | With the change to set up pinctrl after relocation, link fails to boot. Add a special case in the link code to handle this. Fixes: d8906c1f (x86: Probe pinctrl driver in cpu_init_r()) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: quark: Introduce ACPI global NVSBin Meng2016-07-12-0/+7
| | | | | | | | | | | | | | | | This introduces quark-specific ACPI global NVS structure, defined in both C header file and ASL file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Introduce ACPI global NVSBin Meng2016-07-12-0/+26
| | | | | | | | | | | | | | | | | | | | This introduces baytrail-specific ACPI global NVS structure, defined in both C header file and ASL file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Introduce a Kconfig option for the internal UARTBin Meng2016-07-12-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | There are quite a number of BayTrail boards that uses an external SuperIO chipset to provide the legacy UART. For such cases, it's better to have a Kconfig option to enable the internal UART. So far BayleyBay and MinnowMax boards are using internal UART as the U-Boot console, enable this on these two boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: fdt: Drop the unused compatible strings in fdtdecSimon Glass2016-07-11-6/+0
|/ | | | | | | | We have drivers for several more devices now, so drop the strings which are no-longer used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coreboot: Remove the dummy pch driverBin Meng2016-06-29-27/+0
| | | | | | | | | There is a dummy pch driver in the coreboot directory. This causes drivers of its children fail to function due to empty ops. Remove the whole file since it is no longer needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Probe pinctrl driver in cpu_init_r()Bin Meng2016-06-12-0/+5
| | | | | | | | | | | | | | | | | | | | | | At present pinctrl driver gets probed in ich6_gpio driver's probe routine, which has two issues: - Pin's PADs only gets configured when GPIO driver is probed, which is not done by default. This leaves the board in a partially functional state as we must initialize PADs correctly to get perepherals fully working. - The probe routine of pinctrl driver is called multiple times, as normally there are multiple GPIO controllers. It should really be called just once. Move the call to syscon_get_by_driver_data() from ich6_gpio driver to cpu_init_r(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com>
* x86: baytrail: acpi: Fix I/O APIC ID in the MADT tableBin Meng2016-05-30-1/+1
| | | | | | | | So far this is hardcoded to 2, but it should really be read from the I/O APIC register. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: quark: Generate ACPI FADT/MADT tablesBin Meng2016-05-30-0/+164
| | | | | | | Generate quark platform-specific FADT/MADT tables. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: broadwell: Correct I/O APIC IDBin Meng2016-05-23-1/+2
| | | | | | | | | Currently ID 2 is assgined to broadwell I/O APIC, however per chromebook_samus.dts 2 is the core#2 LAPIC ID. Now we change I/O APIC ID to 4 to avoid conflict. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: quark: Assign a unique I/O APIC IDBin Meng2016-05-23-0/+4
| | | | | | | | | | | | | | | | | | | | | | | After power-on, both LAPIC and I/O APIC appear with the same APIC ID zero, which creates an ID conflict. When generating MP table, U-Boot reports zero as the LAPIC ID in the processor entry, and zero as the I/O APIC ID in the I/O APIC as well as the I/O interrupt assignment entries. Such MP table confuses Linux kernel and finally a kernel panic is seen during boot: BUG: unable to handle kernel paging request at ffff9000 IP: [<c101d462>] native_io_apic_write+0x22/0x30 *pdpt = 00000000014fb001 *pde = 00000000014ff067 *pte = 0000000000000000 Oops: 0002 [#1] Modules linked in: Pid: 1, comm: swapper Tainted: G W 3.8.7 #3 intel galileo/galileo EIP: 0060:[<c101d462>] EFLAGS: 00010086 CPU: 0 EIP is at native_io_apic_write+0x22/0x30 ... Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Call lapic_setup() in interrupt_init()Bin Meng2016-05-23-7/+5
| | | | | | | Let's configure LAPIC in a common place - interrupt_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Remove SMP limitation in lapic_setup()Bin Meng2016-05-23-6/+1
| | | | | | | | | At present LAPIC is enabled and configured as virtual wire mode in lapic_setup() only when CONFIG_SMP is on. This limitation is however not necessary as for uniprocessor this is still needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Don't touch IA32_APIC_BASE MSR on Intel QuarkBin Meng2016-05-23-12/+16
| | | | | | | | | | | Intel Quark processor core provides an integrated Local APIC but does not support the IA32_APIC_BASE MSR. As a result, the Local APIC is always globally enabled and the Local APIC base address is fixed at 0xfee00000. Attempting to access the IA32_APIC_BASE MSR causes a general protection fault. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Reserve configuration tables in high memoryBin Meng2016-05-23-3/+8
| | | | | | | When SeaBIOS is on, reserve configuration tables in reserve_arch(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Unify reserve_arch() for all x86 boardsBin Meng2016-05-23-27/+12
| | | | | | | | Instead of asking each platform to provide reserve_arch(), supply it in arch/x86/cpu/cpu.c in a unified way. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Fix up PIRQ routing table checksum earlierBin Meng2016-05-23-0/+4
| | | | | | | | | | | | | | | | PIRQ routing table checksum is fixed up in copy_pirq_routing_table(), which is fine if we only write the configuration table once. But with the SeaBIOS case, when we write the table for the second time, the checksum will be fixed up to zero per the checksum algorithm, which is caused by the checksum field not being zero before fix up, since the checksum has already been calculated in the first run. To fix this, move the checksum fixup to create_pirq_routing_table(), so that copy_pirq_routing_table() only does what its function name suggests: copy the table to somewhere else. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Call board_final_cleanup() in last_stage_init()Bin Meng2016-05-23-9/+21
| | | | | | | | | | | At present board_final_cleanup() is called before booting a Linux kernel. This actually needs to be done before booting anything, like SeaBIOS, VxWorks or Windows. Move the call to last_stage_init() instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: qemu: rename qemu/acpi_table.cMiao Yan2016-05-23-2/+1
| | | | | | | | Rename qemu/acpi_table.c to qemu/e820.c, because ACPI stuff is moved to qfw core, this file only contains code for installing e820 table. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cmd: qfw: bring ACPI generation code into qfw coreMiao Yan2016-05-23-209/+0
| | | | | | | | Loading ACPI table from QEMU's fw_cfg interface is not x86 specific (ARM64 may also make use of it). So move the code to common place. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]Miao Yan2016-05-23-4/+4
| | | | | | | Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: add comment about qfw register endiannessMiao Yan2016-05-23-1/+8
| | | | | | | This patch adds some comments about qfw register endianness for clarity. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: move x86 specific operations out of qfw coreMiao Yan2016-05-23-1/+38
| | | | | | | | | | | The original implementation of qfw includes several x86 specific operations, like directly calling outb/inb and using some inline assembly code which prevents it being ported to other architectures. This patch adds callback functions and moves those to arch/x86/ Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: split qfw command interface and qfw coreMiao Yan2016-05-23-3/+6
| | | | | | | | | | | | This patch splits qfw command interface and qfw core function into two files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core. Now when qfw command interface is enabled, it will automatically select qfw core. This patch also makes the ACPI table generation select CONFIG_QFW. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-08 08:58:01 +0000