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* x86: crownbay: Add SPI flash supportBin Meng2014-12-18-1/+25
* x86: Use consistent name XXX_ADDR for binary blob flash addressBin Meng2014-12-18-5/+5
* x86: Add queensbay and crownbay Kconfig filesBin Meng2014-12-18-0/+79
* x86: Enable the queensbay cpu directory buildBin Meng2014-12-18-0/+1
* x86: Convert microcode format to device-tree-onlySimon Glass2014-12-18-7/+4
* x86: Add basic support to queensbay platform and crownbay boardBin Meng2014-12-18-0/+323
* x86: Correct problems in the microcode loadingSimon Glass2014-12-18-10/+15
* x86: ivybridge: Update the microcodeSimon Glass2014-12-18-0/+2
* x86: Support Intel FSP initialization path in start.SBin Meng2014-12-13-0/+14
* x86: Add post failure codes for bist and carBin Meng2014-12-13-0/+1
* x86: queensbay: Adapt FSP support codesBin Meng2014-12-13-17/+27
* x86: Initial import from Intel FSP release for Queensbay platformBin Meng2014-12-13-0/+426
* x86: Clean up asm-offsetsBin Meng2014-12-13-1/+2
* Replace <compiler.h> with <linux/compiler.h>Masahiro Yamada2014-12-08-1/+2
* x86: Add initial video device init for Intel GMASimon Glass2014-11-25-1/+925
* x86: Add GDT descriptors for option ROMsSimon Glass2014-11-25-3/+6
* x86: ivybridge: Add northbridge init functionsSimon Glass2014-11-25-0/+191
* x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+521
* x86: Add LAPIC setup codeSimon Glass2014-11-25-0/+58
* x86: Drop old CONFIG_INTEL_CORE_ARCH codeSimon Glass2014-11-25-28/+0
* x86: Refactor interrupt_init()Bin Meng2014-11-25-6/+20
* x86: Remove cpu_init_r() for x86Bin Meng2014-11-25-6/+0
* x86: Call cpu_init_interrupts() from interrupt_init()Bin Meng2014-11-25-2/+0
* x86: Add Intel speedstep and turbo mode codeSimon Glass2014-11-25-0/+99
* x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+33
* x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+32
* x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+246
* x86: ivybridge: Add additional LPC initSimon Glass2014-11-25-1/+528
* x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+124
* x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-25-0/+140
* x86: pci: Add handlers before and after a PCI hose scanSimon Glass2014-11-25-0/+12
* x86: Factor out common values in the link scriptSimon Glass2014-11-25-7/+12
* x86: Ensure that all relocation data is included in the imageSimon Glass2014-11-25-1/+3
* x86: Remove board_early_init_r()Simon Glass2014-11-25-11/+0
* x86: Add ivybridge directory to MakefileSimon Glass2014-11-25-0/+2
* Merge git://git.denx.de/u-boot-x86Tom Rini2014-11-24-125/+2595
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| * x86: ivybridge: Implement SDRAM initSimon Glass2014-11-21-5/+1037
| * x86: ivybridge: Add LAPIC supportSimon Glass2014-11-21-0/+3
| * x86: Make show_boot_progress() commonSimon Glass2014-11-21-24/+24
| * x86: ivybridge: Add early init for PCH devicesSimon Glass2014-11-21-0/+287
| * x86: ivybridge: Perform Intel microcode update on bootSimon Glass2014-11-21-0/+157
| * x86: ivybridge: Check BIST value on bootSimon Glass2014-11-21-0/+16
| * x86: ivybridge: Perform initial CPU setupSimon Glass2014-11-21-0/+130
| * x86: Tidy up coreboot header usageSimon Glass2014-11-21-6/+6
| * x86: ivybridge: Add early LPC init so that serial worksSimon Glass2014-11-21-0/+61
| * x86: pci: Allow configuration before relocationSimon Glass2014-11-21-0/+50
| * x86: ivybridge: Enable PCI in early initSimon Glass2014-11-21-0/+67
| * x86: Support use of PCI before relocationSimon Glass2014-11-21-0/+21
| * x86: Refactor PCI to permit alternate initSimon Glass2014-11-21-15/+35
| * x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass2014-11-21-2/+162
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