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path: root/arch/x86/cpu/ivybridge
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* x86: Use consistent name XXX_ADDR for binary blob flash addressBin Meng2014-12-18-1/+1
* x86: Correct problems in the microcode loadingSimon Glass2014-12-18-10/+15
* x86: ivybridge: Update the microcodeSimon Glass2014-12-18-0/+2
* x86: Add post failure codes for bist and carBin Meng2014-12-13-0/+1
* x86: Add initial video device init for Intel GMASimon Glass2014-11-25-1/+925
* x86: ivybridge: Add northbridge init functionsSimon Glass2014-11-25-0/+191
* x86: Add init for model 206AX CPUSimon Glass2014-11-25-0/+521
* x86: ivybridge: Set up XHCI USBSimon Glass2014-11-25-0/+33
* x86: ivybridge: Set up EHCI USBSimon Glass2014-11-25-0/+32
* x86: ivybridge: Add SATA initSimon Glass2014-11-25-0/+246
* x86: ivybridge: Add additional LPC initSimon Glass2014-11-25-1/+528
* x86: ivybridge: Add PCH initSimon Glass2014-11-25-0/+124
* x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-25-0/+140
* x86: ivybridge: Implement SDRAM initSimon Glass2014-11-21-1/+1031
* x86: ivybridge: Add LAPIC supportSimon Glass2014-11-21-0/+3
* x86: ivybridge: Add early init for PCH devicesSimon Glass2014-11-21-0/+287
* x86: ivybridge: Perform Intel microcode update on bootSimon Glass2014-11-21-0/+157
* x86: ivybridge: Check BIST value on bootSimon Glass2014-11-21-0/+16
* x86: ivybridge: Perform initial CPU setupSimon Glass2014-11-21-0/+130
* x86: ivybridge: Add early LPC init so that serial worksSimon Glass2014-11-21-0/+61
* x86: ivybridge: Enable PCI in early initSimon Glass2014-11-21-0/+67
* x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass2014-11-21-2/+162
* x86: Add chromebook_link boardSimon Glass2014-11-21-0/+262
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