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path: root/arch/x86/cpu/ivybridge/lpc.c
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* x86: ivybridge: Drop the SMM-locking codeSimon Glass2016-01-24-57/+0
| | | | | | | | U-Boot does not support SMM yet, so we can drop this code. It is easy to bring back when needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert pch.c to use DM PCI APISimon Glass2016-01-24-5/+5
| | | | | | | Convert this file to use the driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert lpc init code to DM PCI APISimon Glass2016-01-24-63/+66
| | | | | | | | Adjust this code to use the driver model PCI API. This is all called through lpc_init_extra(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move LPC init into the LPC probe() methodSimon Glass2016-01-24-8/+9
| | | | | | | | Drop the lpc_init_extra() function and just use the post-relocation LPC probe() instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move lpc_enable() into gma.cSimon Glass2016-01-24-7/+0
| | | | | | | | This graphics init code is best placed in the gma init code. Move the code and drop the function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move GPIO init to the LPC init() methodSimon Glass2016-01-24-0/+3
| | | | | | | This init can happen in the driver also. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move sandybridge init to the lpc probe() methodSimon Glass2016-01-24-1/+18
| | | | | | | | The watchdog can be reset later when probing the LPC after relocation. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Rename lpc_init() to lpc_init_extra()Simon Glass2016-01-24-1/+1
| | | | | | | | In preparation for adding an init() method to the LPC uclass, rename this existing function so that it will not conflict. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move more init to the probe() functionSimon Glass2016-01-24-0/+43
| | | | | | | | Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Move lpc_early_init() to probe()Simon Glass2016-01-24-7/+25
| | | | | | | | Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Set up the LPC device using driver modelSimon Glass2016-01-24-0/+6
| | | | | | | | | | Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove HAVE_ACPI_RESUMEBin Meng2015-12-09-9/+0
| | | | | | | | | These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Enable DM RTC support for all x86 boardsBin Meng2015-07-28-1/+0
| | | | | | | | Add a RTC node in the device tree to enable DM RTC support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> (Squashed in 'x86: Fix RTC build error on ivybridge')
* x86: chromebook_link: dts: Add PCH and LPC devicesSimon Glass2015-04-18-1/+12
| | | | | | | | | | | | The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: x86: pci: Convert chromebook_link to use driver model for pciSimon Glass2015-04-18-0/+1
| | | | | | | | | | | | | | | | Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a x86_ prefix to the x86-specific PCI functionsSimon Glass2015-04-16-37/+37
| | | | | | | | | | | | These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Add additional LPC initSimon Glass2014-11-25-1/+522
| | | | | | | Set up all the remaining pieces of the LPC (low-pin-count) peripheral in PCH (Peripheral Controller Hub). Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Add early LPC init so that serial worksSimon Glass2014-11-21-0/+48
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>
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