arm-boot/u-boot-imx.git - U-boot NXP imx6

	Commit message (Collapse)	Author	Age	Lines
*	x86: Add post failure codes for bist and car	Bin Meng	2014-12-13	-0/+1
\| \| \| \| \|	Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
*	x86: ivybridge: Add LAPIC support	Simon Glass	2014-11-21	-0/+3
\| \| \| \| \| \| \| \|	The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
*	x86: ivybridge: Add early init for PCH devices	Simon Glass	2014-11-21	-0/+141
\| \| \| \| \| \| \|	Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
*	x86: ivybridge: Perform Intel microcode update on boot	Simon Glass	2014-11-21	-0/+5
\| \| \| \| \| \| \|	Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
*	x86: ivybridge: Check BIST value on boot	Simon Glass	2014-11-21	-0/+16
\| \| \| \| \| \| \|	The built-in self test value should be checked before we continue booting. Refuse to continue if there is something wrong. Signed-off-by: Simon Glass <sjg@chromium.org>
*	x86: ivybridge: Perform initial CPU setup	Simon Glass	2014-11-21	-0/+130
\| \| \| \| \| \| \|	Set up the flex ratio (controls speed versus heat output) and a few other very early things. Signed-off-by: Simon Glass <sjg@chromium.org>
*	x86: ivybridge: Add early LPC init so that serial works	Simon Glass	2014-11-21	-0/+12
\| \| \| \| \| \| \| \|	The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>
*	x86: ivybridge: Enable PCI in early init	Simon Glass	2014-11-21	-0/+6
\| \| \| \| \| \|	Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
*	x86: chromebook_link: Implement CAR support (cache as RAM)	Simon Glass	2014-11-21	-0/+2
\| \| \| \| \| \| \| \|	Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org>
*	x86: Add chromebook_link board	Simon Glass	2014-11-21	-0/+42
	This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>