Commit message (Expand) | Author | Age | Lines | |
---|---|---|---|---|
* | x86: ivybridge: Update microcode early in boot | Simon Glass | 2015-01-13 | -1/+1 |
* | x86: ivybridge: Drop support for ROM caching | Simon Glass | 2015-01-13 | -25/+0 |
* | x86: Add post failure codes for bist and car | Bin Meng | 2014-12-13 | -0/+1 |
* | x86: ivybridge: Add LAPIC support | Simon Glass | 2014-11-21 | -0/+3 |
* | x86: ivybridge: Add early init for PCH devices | Simon Glass | 2014-11-21 | -0/+141 |
* | x86: ivybridge: Perform Intel microcode update on boot | Simon Glass | 2014-11-21 | -0/+5 |
* | x86: ivybridge: Check BIST value on boot | Simon Glass | 2014-11-21 | -0/+16 |
* | x86: ivybridge: Perform initial CPU setup | Simon Glass | 2014-11-21 | -0/+130 |
* | x86: ivybridge: Add early LPC init so that serial works | Simon Glass | 2014-11-21 | -0/+12 |
* | x86: ivybridge: Enable PCI in early init | Simon Glass | 2014-11-21 | -0/+6 |
* | x86: chromebook_link: Implement CAR support (cache as RAM) | Simon Glass | 2014-11-21 | -0/+2 |
* | x86: Add chromebook_link board | Simon Glass | 2014-11-21 | -0/+42 |