| Commit message (Collapse) | Author | Age | Lines |
|---|
| |
|
|
|
|
|
|
| |
mrccache implementation can be common for all boards. Move it
from ivybridge cpu directory to the common lib directory.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
| |
The memory reference code takes a very long time to 'train' its SDRAM
interface, around half a second. To avoid this delay on every boot we can
store the parameters from the last training sessions to speed up the next.
Add an implementation of this, storing the training data in CMOS RAM and
SPI flash.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
|
|
|
|
|
|
|
| |
Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range
of video devices. Add code to set up the hardware on ivybridge. Part of the
init happens in native code, part of it happens in a 16-bit option ROM for
those nostalgic for the 1970s.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
|
|
|
|
| |
Add init for the northbridge, another part of the platform controller hub.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
|
|
|
|
| |
Add the setup code for the CPU so that it can be used at full speed.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
|
|
|
|
| |
Add init for XHCI so that high-speed USB can be used.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
|
|
|
|
| |
Add init for EHCI so that USB can be used.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
|
|
|
|
| |
Add code to set up the SATA interfaces on boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
|
|
|
|
| |
Add required init for the Intel Platform Controller Hub in ivybridge.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
|
|
|
|
| |
Add basic setup for the PCH.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs the Intel Management Engine (me.bin) to work. Binary blobs
everywhere: so far we have MRC, ME and microcode.
SDRAM init works by setting up various parameters and calling the MRC. This
in turn does some sort of magic to work out how much memory there is and
the timing parameters to use. It also sets up the DRAM controllers. When
the MRC returns, we use the information it provides to map out the
available memory in U-Boot.
U-Boot normally moves itself to the top of RAM. On x86 the RAM is not
generally contiguous, and anyway some RAM may be above 4GB which doesn't
work in 32-bit mode. So we relocate to the top of the largest block of
RAM we can find below 4GB. Memory above 4GB is accessible with special
functions (see physmem).
It would be possible to build U-Boot in 64-bit mode but this wouldn't
necessarily provide any more memory, since the largest block is often below
4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large
ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit
kernels directly so this does not pose a limitation in that area. Also there
are probably parts of U-Boot that will not work correctly in 64-bit mode.
The MRC is one.
There is some work remaining in this area. Since memory init is very slow
(over 500ms) it is possible to save the parameters in SPI flash to speed it
up next time. Suspend/resume support is not fully implemented, or at least
it is not efficient.
With this patch, link boots to a prompt.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
|
|
|
|
|
| |
Many PCH devices are hard-coded to a particular PCI address. Set these
up early in case they are needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
|
|
|
|
|
| |
Microcode updates are stored in the device tree. Work through these and
apply any that are needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
|
|
|
|
|
|
| |
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
| |
|
|
|
|
| |
Enable PCI so we can access devices that need to be set up before relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
|
|
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.
This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.
Signed-off-by: Simon Glass <sjg@chromium.org>
|
