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* | powerpc/mpc85xx:Disable non DDR LAWs before init_lawPrabhakar Kushwaha2014-04-22-9/+33
| | | | | | | | | | | | | | | | | | Before parsing LAW table i.e. init_law, boot loader should disable all previous LAWs except DDR LAWs which has been created by previous pre boot loader during DDR initialization. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc:Add support of SPL non-relocationPrabhakar Kushwaha2014-04-22-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Current SPL code base has BSS section placed after reset_vector. This means they have to relocate to use the global variables. This put an implicit requirement of having SPL size = Memory/2. To avoid relocation: - Move bss_section within SPL range - Modify relocate_code() Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: Avoid hardcoding in SPL linker scriptPrabhakar Kushwaha2014-04-22-1/+6
| | | | | | | | | | | | | | | | | | | | SPL linker has fix location of bootpg and reset vector with respect to text base. It is not necessary to have fixed locations. Avoid such hardcoding. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: Move LAW_EN define outside of configPrabhakar Kushwaha2014-04-22-1/+2
| | | | | | | | | | | | | | | | | | | | | | LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence both are same. This cause compilation error. So LAW_EN define outside of configs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: Remove QE firmware copy from NANDPrabhakar Kushwaha2014-04-22-13/+0
| | | | | | | | | | | | | | | | | | | | qe_init() does not use data copied from NAND. Thise code is not tested or complied causing compilation error during NAND boot So, remove QE firmware copy from NAND to ddr. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | mpc85xx/t104x: Add deep sleep framework supportTang Yuantian2014-04-22-0/+24
| | | | | | | | | | | | | | | | | | | | When T104x soc wakes up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves before. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | mpc85xx: Add support for the supplement configuration unit registerTang Yuantian2014-04-22-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/cpu/mpc85xx: Add MAC address for layer 2 switchCodrin Ciubotariu2014-04-22-0/+29
| | | | | | | | | | | | | | | | | | | | | | T1040RDB and T1040QDS boards have an integrated l2 switch. The switch needs a MAC address for Layer 2 protocols (MSTP, LLDP, LACP, etc). Setting a MAC address on l2switchaddr will add a MAC in device-tree, under node l2switch. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Cc: York Sun <yorksun@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: Add workaround for erratum A007212York Sun2014-04-22-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun@freescale.com>
* | fsl/usb: Workaround for USB erratum-A007075Nikhil Badola2014-04-22-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | Put a delay of 5 millisecond after reset so that ULPI phy gets enough time to come out of reset. Erratum A007075 applies to following SOCs and their variants, if any P1010 rev 1.0 B4860 rev 1.0, 2.0 P4080 rev 2.0, 3.0 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | driver/ddr/fsl: Add DDR4 support to Freescale DDR driverYork Sun2014-04-22-3/+14
| | | | | | | | | | | | | | Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
* | powerpc/85xx: Fix e6500 L2 cache stash IDsScott Wood2014-04-22-4/+8
| | | | | | | | | | | | | | | | The value written to L2CSR1 didn't match the value written to the device tree. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | QE/U-QE: Add U-QE supportZhao Qiang2014-04-22-5/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and ↵Zhao Qiang2014-04-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDBAneesh Bansal2014-04-22-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDSAneesh Bansal2014-04-22-1/+3
| | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for T2080QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDSAneesh Bansal2014-04-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for T4240QDS and T4160QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDSAneesh Bansal2014-04-22-6/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDSAneesh Bansal2014-04-22-7/+4
| | | | | | | | | | | | | | | | | | | | Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc8xxx: SECURE BOOT- Disable law 0 for non PBL platformsAneesh Bansal2014-04-22-0/+10
| | | | | | | | | | | | | | | | | | ISBC creates a LAW 0 entry for non PBL platforms, which is not disabled before transferring the control to uboot. The LAW 0 entry has to be disabled. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | PPC 85xx: Add qemu-ppce500 machineAlexander Graf2014-04-22-4/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For KVM we have a special PV machine type called "ppce500". This machine is inspired by the MPC8544DS board, but implements a lot less features than that one. It also provides more PCI slots and is supposed to be enumerated by device tree only. This patch adds support for the generic ppce500 machine and tries to rely solely on device tree for device enumeration. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | PPC 85xx: Add ELF entry pointAlexander Graf2014-04-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | We want to be able to directly execute the ELF binary without going through the u-boot.bin one. To know where we have to start executing this ELF binary we have to tell the linker where our entry point is. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | PPC: 85xx: Generalize DDR TLB mapping functionAlexander Graf2014-04-22-15/+40
| | | | | | | | | | | | | | | | | | | | The DDR mapping function really is just a generic virtual -> physical mapping function. Generalize it so it can support any virtual starting offset and IO maps just the same. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | PPC: 85xx: Remove IVOR resetAlexander Graf2014-04-22-76/+0
|/ | | | | | | | | | | There is no need to set IVORs to anything but their default values, so let's leave them where they are. Suggested-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> [York Sun: Add back $(obj)start.S section in mpc8572ds/Makefile] Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc: remove MOUSSE board supportMasahiro Yamada2014-04-18-88/+0
| | | | | | | | | | | Enough time has passed since this board was moved to Orphan. Remove. - Remove board/mousse/* - Remove include/configs/MOUSSE.h - Clean-up defined(CONFIG_MOUSSE) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: remove RPXClassic, RPXlite boards supportMasahiro Yamada2014-04-18-13/+1
| | | | | | | | | | | | | Enough time has passed since these boards were moved to Orphan. Remove. - Remove board/RPXlite/* - Remove board/RPXClassic/* - Remove include/configs/RPXlite.h - Remove include/configs/RPXClassic.h - Clean-up defined(CONFIG_RPXCLASSIC) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: remove ADS860, FADS823, FADS850SAR, FADS860T supportMasahiro Yamada2014-04-18-13/+1
| | | | | | | | | | | Enough time has passed since these boards were moved to Orphan. Remove. - Remove include/configs/{ADS860.h,FADS823.h,FADS850SAR.h,FADS860T.h} - Cleanup defined(CONFIG_ADS), defined(CONFIG_MPC823FADS), defined(CONFIG_MPC850SAR), defined(CONFIG_SYS_DAUGHTERBOARD) - Remove the entries from boards.cfg Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: remove MBX and MBX860T boards supportMasahiro Yamada2014-04-18-25/+0
| | | | | | | | | | | Enough time has passed since these boards were moved to Orphan. Remove. - Remove board/mbx8xx/* - Remove include/configs/{MBX.h,MBX860T.h} - Clean-up if defined(CONFIG_MBX) - Move the entries from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: remove NX823 board supportMasahiro Yamada2014-04-18-3/+0
| | | | | | | | | | | Enough time has passed since this board was moved to Orphan. Remove. - Remove board/nx823/* - Remove include/configs/NX823.h - Clean-up ifdef(CONFIG_NX823) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc8xx: delete an unused source fileMasahiro Yamada2014-04-17-20/+0
| | | | | | | | | References to the wireless keyboard should also be removed from README.console. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* mmc:eSDHC: Workaround for data timeout issue on Txxx SoCHaijun.Zhang2014-04-02-0/+5
| | | | | | | | | | | | | | 1. The Data timeout counter value in eSDHC_SYSCTL register is not working as it should be, so add quirks to enable this workaround to fix it to the max value 0xE. 2. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround. * Update of patch for change mmc interface by Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* kbuild: rename OBJTREE to objtreeMasahiro Yamada2014-03-12-1/+1
| | | | | | | | | | | Prior to Kbuild, $(OBJTREE) was used for pointing to the top of build directory with absolute path. In Kbuild style, $(objtree) is used instead. This commit renames OBJTREE to objtree and delete the defition of OBJTREE. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* kbuild: rename TOPDIR to stctreeMasahiro Yamada2014-03-12-1/+1
| | | | | | | | | | | | Prior to Kbuild, $(TOPDIR) or $(SRCTREE) was used for pointing to the top of source directory. (No difference between the two.) In Kbuild style, $(srctree) is used instead. This commit renames TOPDIR to srctree and delete the defition of TOPDIR. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* usb: create common header virtual root hub descriptorsStephen Warren2014-03-10-196/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many USB host controller drivers contain almost identical copies of the same virtual root hub descriptors. Put these into a common file to avoid duplication. Note that there were some very minor differences between the descriptors in the various files, such as: - USB 1.0 vs. USB 1.1 - Manufacturer/Device ID - Max packet size - String content I assume these aren't relevant. Cc: Thomas Lange <thomas@corelatus.se> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Eric Millbrandt <emillbrandt@coldhaus.com> Cc: Pierre Aubert <p.aubert@staubli.com> Cc: Stefan Roese <sr@denx.de> Cc: Daniel Hellstrom <daniel@gaisler.com> Cc: Denis Peter <d.peter@mpl.ch> Cc: Rodolfo Giometti <giometti@linux.it> Cc: Zhang Wei <wei.zhang@freescale.com> Cc: Mateusz Zalega <m.zalega@samsung.com> Cc: Remy Bohmer <linux@bohmer.net> Cc: Markus Klotzbuecher <mk@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: C Nauman <cnauman@diagraph.com> Cc: David Müller <d.mueller@elsoft.ch> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Thomas Abraham <t-abraham@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Andrew Murray <amurray@embedded-bits.co.uk> Cc: Matej Frančeškin <matej.franceskin@comtrade.com> Cc: Cliff Cai <cliff.cai@analog.com> Cc: Bryan Wu <cooloney@gmail.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-03-07-2/+216
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| * powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040Priyanka Jain2014-03-07-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040 SoC has SCFG (Supplement Configuration) Block which provides chip specific configuration and status support. The base address of SCFG block in T1040 is 0xfc000. SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register) at offset 0x28. Add definition of -SCFG block -SCFG_PIXCLKCR register -Bits definition of SCFG_PIXCLK register Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * bootstage: powerpc: support fdt stash and reportingMela Custodio2014-03-07-0/+7
| | | | | | | | | | | | | | | | | | This implements stashing of bootstage timing data to FDT and automatic timing reporting. To enable define CONFIG_BOOTSTAGE_FDT and CONFIG_BOOTSTAGE_REPORT respectively. Signed-off-by: Rommel G Custodio <sessyargc+u-boot@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/usb: Workaround for erratum-A006261Suresh Gupta2014-03-07-0/+107
| | | | | | | | | | | | | | | | | | | | | | USB spec says that the minimum disconnect threshold should be over 525 mV. However, internal USB PHY threshold value is below this specified value. Due to this some devices disconnect at run-time. Hence, phy settings are tweaked to increased disconnect threshold to be above 525mV by using this workaround. Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/b4860: Add workaround for errata A006384 and A006475Shaveta Leekha2014-03-07-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * B4860/B4420: Add PLL_NUM define for B4420/B4860 to use SerDes2 Refclks ↵Shaveta Leekha2014-03-07-0/+2
| | | | | | | | | | | | | | | | | | | | re-configuration B4860 has two PLL per SerDes whereas B4420 has one PLL per SerDes, add their defines in arch/powerpc/include/asm/config_mpc85xx.h Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * 85xx/b4860: Alternate serdes protocols for B4860/B4420poonam aggrwal2014-03-07-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On B4860 and B4420, some serdes protocols can be used with LC VCO as well as Ring VCO options. Addded Alternate options with LC VCO for such protocols. For example protocol 0x2a on srds 1 becomes 0x29 if it is LC VCO. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/b4860qds: Add support to make PCIe SATA work on B4860QDSShaveta Leekha2014-03-07-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | 1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/b4860qds: Add support to make Aurora work on B4860QDSShaveta Leekha2014-03-07-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | 1) Add new SerDes1 protocols having Aurora in them 2) Add VSC cross point connections for Aurora to work with CPRI and SGMIIs 3) Configure VSC crossbar switch to connect SerDes1 lanes to aurora on board, by checking SerDes1 protocols 4) SerDes1 Refclks have been set properly to make Aurora, CPRI and SGMIIs to work together properly Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | kbuild: move "checkgcc4" to PowerPC archprepareMasahiro Yamada2014-03-07-1/+10
| | | | | | | | | | | | | | | | | | | | "checkgcc4" is used only for PowerPC. Move it to arch/powerpc/config.mk. To make sure gcc is new enough before beginning build, run "checkgcc4" during "archprepare". Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | powerpc: mpc8260: consolidate CONFIG_MPC8260 and CONFIG_8260Masahiro Yamada2014-03-07-16/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, CONFIG_MPC8260 and CONFIG_8260 were used mixed-up. All boards with mpc8260 cpu defined both of them: - CONFIG_MPC8260 was defined in board config headers and include/common.h - CONFIG_8260 was defined arch/powerpc/cpu/mpc8260/config.mk We do not need to have both of them. This commit keeps only CONFIG_MPC8260. This commit does: - Delete CONFIG_8260 and CONFIG_MPC8260 definition in config headers and include/common.h - Rename CONFIG_8260 to CONFIG_MPC8260 in arch/powerpc/cpu/mpc8260/config.mk. - Rename #ifdef CONFIG_8260 to #ifdef CONFIG_MPC8260 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de>
* | kbuild: add CONFIG_ prefix to USE_PRIVATE_LIBGCCMasahiro Yamada2014-03-07-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, USE_PRIVATE_LIBGCC was defined in arch-specific config.mk and referenced in arch/$(ARCH)/lib/Makefile. We are not happy about parsing config.mk again and again. We have to keep the same behavior with a different way. By adding "CONFIG_" prefix, this macro appears in include/autoconf.mk, include/spl-autoconf.mk. (And treating USE_PRIVATE_LIBGCC as CONFIG macro is reasonable enough.) Tegra SoC family defined USE_PRIVATE_LIBGCC as "yes" in arch/arm/cpu/arm720t/tegra*/config.mk, whereas did not define it in arch/arm/cpu/armv7/tegra*/config.mk. It means Tegra enables PRIVATE_LIBGCC only for SPL. We can describe the same behavior by adding #ifdef CONFIG_SPL_BUILD # define CONFIG_USE_PRIVATE_LIBGCC #endif to include/configs/tegra-common.h. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com>
* | ppc4xx: Remove 4xx NAND booting supportStefan Roese2014-03-07-142/+5
|/ | | | | | | | | | | | | | | | | As ppc4xx currently only supports the deprecated nand_spl infrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely. This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tirumala Marri <tmarri@apm.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* kbuild: fix CROSS_COMPILE settings in config.mkMasahiro Yamada2014-03-04-1/+3
| | | | | | | | | | | | | | | | The syntax CROSS_COMIPLE ?= <cross_compiler_prefix> does not work because config.mk is parsed after exporting CROSS_COMPILE. Like Linux Kernel's arch/$(ARCH)/Makefile, we must write as follows: ifeq ($(CROSS_COMPILE),) CROSS_COMPILE := <cross_compiler_prefix> endif Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-02-25-3/+5
|\ | | | | | | | | | | | | With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
| * powerpc/t208x: some update to support t2081Shengzhou Liu2014-02-24-3/+5
| | | | | | | | | | | | | | | | | | | | - fix serdes definition for t2081. - fix clock speed for t2081. - update ids, as CONFIG_FSL_SATA_V2 is needed only for t2080, T2081 has no SATA. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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