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| * powerpc: mpc8541: Remove macro CONFIG_MPC8541York Sun2016-11-23-8/+12
| | | | | | | | | | | | | | Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: mpc8540: Remove macro CONFIG_MPC8540York Sun2016-11-23-6/+10
| | | | | | | | | | | | | | Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig optionYork Sun2016-11-23-5/+9
| | | | | | | | | | | | | | Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: C29XPCIE: Remove macro CONFIG_C29XPCIEYork Sun2016-11-23-3/+3
| | | | | | | | | | | | Use CONFIG_TARGET_C29XPCIE instead. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig optionYork Sun2016-11-23-9/+13
| | | | | | | | | | | | | | Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: BSC9132QDS: Remove CONFIG_BSC9132QDS macroYork Sun2016-11-23-2/+2
| | | | | | | | | | | | | | Use CONFIG_TARGET_BSC9132QDS from Kconfig option, remove CONFIG_BSC9132QDS macro. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig optionsYork Sun2016-11-23-15/+23
| | | | | | | | | | | | | | | | | | Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132 Kconfig options. Also drop #ifdef in BSC9131RDB.h since it is redundant. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: MPC8544: Move CONFIG_MPC8544 to Kconfig optionYork Sun2016-11-23-4/+9
| | | | | | | | | | | | Replace CONFIG_MPC8544 with ARCH_MPC8544 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig optionYork Sun2016-11-23-7/+13
| | | | | | | | | | | | Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com>
* | fsl: serdes: fix a deadloop issue for P4080Hou Zhiqiang2016-11-21-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | This deadloop is introduced by commit: 71fe222 fsl: serdes: ensure accessing the initialized maps of serdes protocol deadloop detail: cpu_init_r => fsl_serdes_init => p4080_erratum_serdes_a005 => is_serdes_configured => fsl_serdes_init Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | powerpc: mpc512x: Add support for get_svr() for mpc512x devicesSriram Dash2016-11-21-0/+5
|/ | | | | | | | Defines get_svr() for mpc512x devices Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Fix spelling of "resetting".Vagrant Cascadian2016-10-31-2/+4
| | | | | | | | Cover-Letter: Fixes several spelling errors for the words "resetting", "extended", "occur", and "multiple". Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* arch: powerpc: Remove unused dts frequency fixup for lbc_clkPrabhakar Kushwaha2016-10-14-11/+0
| | | | | | | | | | lbc_clk is used to fixup dts as "bus frequency". It is not being used by Linux IFC and eLBC driver. So remove unused "bus frqeuency" fix-up of devicre tree. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Various, accumulated typos collected from around the tree.Robert P. J. Day2016-10-06-2/+2
| | | | | | | | | | | | | | | | | | | | | Fix various misspellings of: * deprecated * partition * preceding,preceded * preparation * its versus it's * export * existing * scenario * redundant * remaining * value * architecture Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Stefan Roese <sr@denx.de>
* spl: Add a parameter to jump_to_image_linux()Simon Glass2016-10-06-2/+2
| | | | | | | | Instead of using the global spl_image variable, pass the required struct in as an argument. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* mpc85xx: powerpc: usb: Update the list of Socs afftected by erratum A006261Sriram Dash2016-09-28-3/+1
| | | | | | | | | | | | | | | | | Apply the erratum A006261 for the following Socs: P2041 rev 2.0, P2040 rev 2.0, P5040 rev 2.0, 2.1 Do not apply erratum A006261 for the following Socs: T4160, T4080, T1040, T1042, T1020, T1022, T2080, T2081 Erratum A006261 is applicable for the following Socs: P1010(1.0, 2.0), P2041(1.0, 1.1, 2.0, 2.1), P2040(1.0, 1.1, 2.0, 2.1), P3041(1.0, 1.1, 2.0, 2.1), P5010(1.0, 2.0), P5020(1.0, 2.0), P5021(1.0, 2.0), T4240(1.0, 2.0), P5040(1.0,2.0,2.1). Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010Sriram Dash2016-09-28-0/+3
| | | | | | | | | CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy offset are set to enable the initial setting of Usb Phy for P1010. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* mpc85xx: powerpc: usb: Modified the erratum A006261 according to endiannessSriram Dash2016-09-28-2/+2
| | | | | | | | | | Modifies erratum implementation due to the fact that P3041, P5020, and P5040 are all big endian for the USB PHY registers, but they were specified little endian. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-09-26-7/+227
|\ | | | | | | | | | | | | trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * fsl: serdes: ensure accessing the initialized maps of serdes protocolHou Zhiqiang2016-09-14-7/+227
| | | | | | | | | | | | | | | | | | | | | | | | Up to now, the function is_serdes_configed() doesn't check if the map of serdes protocol is initialized before accessing it. The function is_serdes_configed() will get wrong result when it was called before the serdes protocol maps initialized. As the first element of the map isn't used for any device, so use it as the flag to indicate if the map has been initialized. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Remove arch/${ARCH}/include/asm/errno.hMasahiro Yamada2016-09-23-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike Linux, nothing about errno.h is arch-specific in U-Boot. As you see, all of arch/${ARCH}/include/asm/errno.h is just a wrapper of <asm-generic/errno.h>. Actually, U-Boot does not export headers to user-space, so we just have to care about the consistency in the U-Boot tree. Now all of include directives for <asm/errno.h> are gone. Deprecate <asm/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
* | treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-23-7/+7
| | | | | | | | | | | | | | | | | | | | | | Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
* | treewide: use #include <...> to include public headersMasahiro Yamada2016-09-23-8/+8
| | | | | | | | | | | | | | | | | | We are supposed to use #include <...> to include headers in the public include paths. We should use #include "..." only for headers in local directories. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | arch, board: squash lines for immediate returnMasahiro Yamada2016-09-23-10/+2
| | | | | | | | | | | | | | | | Remove unneeded variables and assignments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com> Reviewed-by: Angelo Dureghello <angelo@sysam.it>
* | PowerPC: Update MIP405/MIP405T to use Kconfig betterTom Rini2016-09-20-3/+9
| | | | | | | | | | | | | | | | | | | | | | Convert CONFIG_MIP405T from SYS_EXTRA_OPTIONS to a real config There are two boards, MIP405 and MIP405T that have a few differences. Start by checking for CONFIG_TARGET_MIP405. Then introduce CONFIG_TARGET_MIP405T and use that not CONFIG_MIP405T. Next, convert also convert the usage of CONFIG_ISO_STRING to be based on Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Kconfig: Move config IDENT_STRING to KconfigSiva Durga Prasad Paladugu2016-09-20-6/+0
| | | | | | | | | | | | | | | | | | Move the config IDENT_STRING to Kconfig and migrate all boards [sivadur: Migrate zynq boards] Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> [trini: Update configs, add some default to sunxi Kconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
* | Convert CONFIG_SPL_DRIVERS_MISC_SUPPORT to KconfigSimon Glass2016-09-16-3/+0
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_HASH_SUPPORT to KconfigSimon Glass2016-09-16-1/+0
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_CRYPTO_SUPPORT to KconfigSimon Glass2016-09-16-1/+0
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Move existing use of CONFIG_SPL_RSA to KconfigSimon Glass2016-09-16-1/+0
| | | | | | | | | | | | | | A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Move existing use of CONFIG_SPL_DM to KconfigSimon Glass2016-09-16-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Note that quite a few boards defined this options but do not appear to actually use SPL: BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS_SPIFLASH_DDRCLK133_SECURE C29XPCIE_NOR_SECBOOT P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB-PA_NAND_SECBOOT P1010RDB-PA_NOR_SECBOOT P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB-PB_NAND_SECBOOT P1010RDB-PB_NOR_SECBOOT P3041DS_SECURE_BOOT P4080DS_SECURE_BOOT P5020DS_NAND_SECURE_BOOT P5040DS_SECURE_BOOT T1023RDB_SECURE_BOOT T1024QDS_DDR4_SECURE_BOOT T1024QDS_SECURE_BOOT T1024RDB_SECURE_BOOT T1040RDB_SECURE_BOOT T1042D4RDB_SECURE_BOOT T1042RDB_SECURE_BOOT T2080QDS_SECURE_BOOT T2080RDB_SECURE_BOOT T4160QDS_SECURE_BOOT T4240QDS_SECURE_BOOT ls1021aqds_nor_SECURE_BOOT ls1021atwr_nor_SECURE_BOOT ls1043ardb_SECURE_BOOT For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since they apparently don't have an SPL, this should not matter. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: fsl: Adjust ordering of #ifndef CONFIG_SPL_BUILDSimon Glass2016-09-16-1/+2
|/ | | | | | | | | | | | The secure boot header files incorrectly define SPL options only if CONFIG_SPL_BUILD is defined. This means that the options are only enabled in an SPL build, and not with a normal 'make xxx_defconfig'. This means that moveconfig.py cannot work, since it sees the options as disabled even when they may be manually enabled in an SPL build. Fix this by changing the order. Signed-off-by: Simon Glass <sjg@chromium.org>
* net: mii: Changes not made by spatchJoe Hershberger2016-08-15-7/+4
| | | | | | | | | | | | | If the functions passed to the registration function are not in the same C file (extern) then spatch will not handle the dependent changes. Make those changes manually. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> For the 4xx related files: Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* net: mii: Fix changes made by spatchJoe Hershberger2016-08-15-2/+4
| | | | | | | Some of the changes were a bit too complex. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* net: mii: Use spatch to update miiphy_registerJoe Hershberger2016-08-15-17/+43
| | | | | | | Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* ppc4xx: Fix platform supportDirk Eibach2016-08-09-21/+45
| | | | | | | | | | | | | | | Commit "ecc3066 Fix board init code to respect the C runtime environment" broke platform support for ppc4xx. start.S prepares a stackframe that is later rendered unusable by appending the reserved space for global data. Instead the reserved space has to be put first. Then the stackframe can be pushed. I can only test the 405EP OCM case. At least all other ppc4xx boards still build. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* treewide: move CONFIG_PHYS_64BIT to KconfigMasahiro Yamada2016-08-05-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | We need to ensure that CONFIG_PHYS_64BIT is configured via Kconfig so that it is always available to the build system. Otherwise we can run into cases where we have inconsistent sizes of certain attributes. Ravi Babu reported offset mismatch of struct dwc3 across files since commit 95ebc253e6d4 ("types.h: move and redefine resource_size_t"). Since the commit, resource_addr_t points to phys_addr_t, whose size is dependent on CONFIG_PHYS_64BIT for ARM architecture. I tried my best to use "select" where possible (for example, ARMv8 architecture) because I think this kind of option is generally user- unconfigurable. However, I see some of PowerPC boards have 36BIT defconfigs as well as 32BIT ones. I moved CONFIG_PHYS_64BIT to the defconfigs for such boards. CONFIG_36BIT is no longer referenced, so all of the defines were removed from CONFIG_SYS_EXTRA_OPTIONS. Fixes: 95ebc253e6d4 ("types.h: move and redefine resource_size_t") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Ravi Babu <ravibabu@ti.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc/mpc85xx: Update erratum workaround for A006379York Sun2016-08-02-1/+1
| | | | | | | | Update erratum workaround for A006379 to set register CPCHDBCR0 with value 0x001e0000, replacing the old value 0x003c0000. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Dave Liu <dave.liu@nxp.com>
* Merge git://git.denx.de/u-boot-mpc86xxTom Rini2016-07-26-1/+1
|\
| * powerpc/86xx: Pass -mcpu=7400 to GCCScott Wood2016-07-25-1/+1
| | | | | | | | | | | | | | | | Without this, GCC uses the toolchain default, which may be incompatible with -maltivec. Signed-off-by: Scott Wood <oss@buserror.net> Reviewed-by: York Sun <york.sun@nxp.com>
* | SECURE_BOOT: Enable SD as a source for bootscriptSumit Garg2016-07-26-2/+2
|/ | | | | | | | | | | Add support for reading bootscript and bootscript header from SD. Also renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and NOR flash. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc/mpc85xx: T104x: Add nand secure boot targetSumit Garg2016-07-21-6/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPLSumit Garg2016-07-21-1/+46
| | | | | | | | | | | | | | | | As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-3/+3
| | | | | | | | | | | | | | | | | | | Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* dm: gpio: MPC85XX GPIO platform data supportHamish Martin2016-07-11-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a platform data structure for the MPC85XX GPIO driver to allow use of the driver without device tree. Users should define the GPIO blocks for their platform like this: struct mpc85xx_gpio_plat gpio_blocks[] = { { .addr = 0x130000, .ngpios = 32, }, { .addr = 0x131000, .ngpios = 32, }, }; U_BOOT_DEVICES(my_platform_gpios) = { { "gpio_mpc85xx", &gpio_blocks[0] }, { "gpio_mpc85xx", &gpio_blocks[1] }, }; This is intended to build upon the recent submission of the base MPC85XX driver from Mario Six. We need to use that new driver without dts support and this patch gives us that flexibility. This has been tested on a Freescale T2080 CPU, although only the first GPIO block. Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Reviewed-by: Mario Six <mario.six@gdsys.cc> Tested-by: Mario Six <mario.six@gdsys.cc> Acked-by: Simon Glass <sjg@chromium.org>
* powerpc: mpc85xx: Do not build errata command in SPLMarek Vasut2016-07-05-0/+2
| | | | | | | | | The errata command is useless in SPL, so don't build it. This fixes multiple build failures on PowerPC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: York Sun <york.sun@nxp.com> Fixes: 92623672f9d3 ("fsl: usb: make errata function common for PPC and ARM")
* Remove unneeded remnants of bcopy().Robert P. J. Day2016-06-06-7/+0
| | | | | | | Since bcopy() is no longer used, delete all remaining references to it. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* dm: gpio: Add driver for MPC85XX GPIO controllermario.six@gdsys.cc2016-06-03-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well). Each GPIO bank is identified by its own entry in the device tree, i.e. gpio-controller@fc00 { #gpio-cells = <2>; compatible = "fsl,pq3-gpio"; reg = <0xfc00 0x100> } By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC). The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported. The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* arch/powerpc: Simplify some calculations using ARRAY_SIZE() macro.Robert P. J. Day2016-06-03-14/+14
| | | | | | | | Replace a number of array length calculations with the ARRAY_SIZE() macro, for clarity. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-by: York Sun <york.sun@nxp.com>
* Delete tests of CONFIG_OF_LIBFDT when testing CONFIG_OF_BOARD_SETUPRobert P. J. Day2016-05-27-8/+8
| | | | | | | | | | | | | | | | Since CONFIG_OF_BOARD_SETUP depends on CONFIG_OF_LIBFDT: config OF_BOARD_SETUP bool "Set up board-specific details in device tree before boot" depends on OF_LIBFDT ... remove superfluous tests of CONFIG_OF_LIBFDT when testing for CONFIG_OF_BOARD_SETUP. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> [trini: Typo fix: s/ifdefi/ifdef/] Signed-off-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-11-20 17:30:51 +0000