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* mpc85xx/p1020:Define number of USB controllers used on P1020RDB-PD platformramneek mehresh2014-05-16-0/+2
| | | | | | | | P1020 SoC which has two USB controllers, but only first one is used on this platform. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Added B4460 supportShaveta Leekha2014-05-16-0/+2
| | | | | | | | | | | B4460 differs from B4860 only in number of CPU cores, hence used existing support for B4860. B4460 has 2 PPC cores whereas B4860 has 4 PPC cores. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl/pci: Add workaround for erratum A-005434Chunhe Lan2014-05-16-0/+4
| | | | | | | | | | By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are mapped to 0xF, which is local memory. But for BSC9132, 0xF is CCSR, 0x0 is local memory. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc86xx: Fix boot_flag for calling board_init_f()York Sun2014-05-13-0/+1
| | | | | | | The argument boot_flag of board_inti_f() hasn't been used for powerpc until recent changing to use generic board. Set it to 0 as a proper value. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Fix boot_flag for calling board_init_f()York Sun2014-05-13-5/+8
| | | | | | | | | baord_init_f takes one argument, boot_flag. It has not been used for powerpc, until recently changing to use generic board architecture. The boot flag is added as a return value from cpu_init_f(). Signed-off-by: York Sun <yorksun@freescale.com> CC: Alexander Graf <agraf@suse.de>
* powerpc/mpc85xx: Ignore FDT pointer for non-QEMU in cpu_init_early_f()York Sun2014-05-13-0/+2
| | | | | | | | | The pointer of device tree comes from r3 for QEMU. This is not the case for normal SoCs out of reset. Having gd->fdt_blob as 0 is important for other functions to detect the non-existence of device tree. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alexander Graf <agraf@suse.de>
* powerpc/mpc85xx: Update TLB CAMs in relocated modeAlexander Graf2014-05-13-0/+1
| | | | | | | | We want to use the TLB mapping helpers in relocated mode as well. These helpers need to have awareness of already occupied TLB entries. We already had them in sync in non-relocated mode, but need to resync them when we move into relocated. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC 85xx QEMU: Don't use HID1Alexander Graf2014-05-13-1/+1
| | | | | | | | | | For the QEMU machine type, we can plug in either e500v2, e500mc, e5500 or e6500 style cores into the system. U-boot has to work with all of them. So avoid using HID1 which is not available on e500mc systems to make sure we don't trap on it. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC 85xx QEMU: Always assume 1 coreAlexander Graf2014-05-13-2/+2
| | | | | | | | | | | | | | | We only need u-boot to bother about a single core in the QEMU machine. Everything that would require additional knowledge of more cores gets handled by QEMU and passed straight into the payload we execute. Because of this setup, it would be counterproductive to enable SMP support in u-boot. We would have to rip CPUs out of already existing spin tables and respin them from u-boot. It would be a pretty big mess. So only assume we have a single core. This fixes errors about CONFIG_MP being disabled. Signed-off-by: Alexander Graf <agraf@suse.de>
* powerpc/85xx: add T4080 SoC supportShengzhou Liu2014-05-13-10/+56
| | | | | | | | The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* powerpc/t208x: enable errata A006261, A006593, A006379Shengzhou Liu2014-05-13-0/+6
| | | | | | | Enable errata A006261, A006593, A006379 for T208x. Additionally enable CONFIG_CMD_ERRATA for T2080RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080RDBAneesh Bansal2014-05-13-0/+1
| | | | | | | | | | | Secure Boot Target is added for T2080RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080RDB. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
* powerpc/mpc85xx: SECURE BOOT- secure boot target for t1040rdbAneesh Bansal2014-05-13-1/+1
| | | | | | | | T1040RDB.h file is removed and a unified file T104xRDB.h is created. Hence macro CONFIG_T1040 is renamed to CONFIG_T104x. Signed-off-by: Gaurav Kumar Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
* powerpc/85xx: Add T4240RDB board supportChunhe Lan2014-05-13-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240RDB board Specification ---------------------------- Memory subsystem: 6GB DDR3 128MB NOR flash 2GB NAND flash Ethernet: Eight 1G SGMII ports Four 10Gbps SFP+ ports PCIe: Two PCIe slots USB: Two USB2.0 Type A ports SDHC: One SD-card port SATA: One SATA port UART: Dual RJ45 ports Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> [York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]
* cosmetic: delete misleading comment /* CONFIG_BOARDDIR */Masahiro Yamada2014-05-12-4/+4
| | | | | | | CONFIG_BOARDDIR is not referenced in these linker scripts. The comment /* CONFIG_BOARDDIR */ is misleading. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* bd_info: remove bi_barudrate member from struct bd_infoMasahiro Yamada2014-05-12-3/+1
| | | | | | | | | | | | | | | | | gd->bd->bi_baudrate is a copy of gd->baudrate. Since baudrate is a common feature for all architectures, keep gd->baudrate only. It is true that bi_baudrate was passed to the kernel in that structure but it was a long time ago. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Cc: Simon Glass <sjg@chromium.org> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de> Acked-by: Michal Simek <monstr@monstr.eu> (For microblaze)
* Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxTom Rini2014-04-25-3/+4
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| * mpc8313, bootcount: mpc8313 has no qe muramHeiko Schocher2014-04-23-3/+4
| | | | | | | | | | | | | | | | mpc831x has no muram, so muram cannot be used for bootcounter function. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | powerpc/mpc85xx:Update FM1 clock select and shift for B4420Prabhakar Kushwaha2014-04-22-2/+2
| | | | | | | | | | | | | | | | B4420 is a personality of B4860. It should have same FM1_CLK_SEK and FM1_CLK_SHIFT as B4860 Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: Add Differential SYSCLK config support T1040Nikhil Badola2014-04-22-0/+26
| | | | | | | | | | | | | | | | | | Adds support for clock sourcing from sysclk(100MHz) for usb on T104xRDB and T1040QDS. This requires changing reference divisor and multiplication factor to derive usb clock from sysclk. Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/85xx: Enhance get_sys_info() to check clocking modevijay rai2014-04-22-8/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx:Avoid fix address of bootpg sectionPrabhakar Kushwaha2014-04-22-2/+12
| | | | | | | | | | | | | | | | | | It is not necessary for bootpg to be present at text + 512KB. With increase of u-boot size (768KB), bootpg section's address cannot be fixed. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx:Disable non DDR LAWs before init_lawPrabhakar Kushwaha2014-04-22-9/+33
| | | | | | | | | | | | | | | | | | Before parsing LAW table i.e. init_law, boot loader should disable all previous LAWs except DDR LAWs which has been created by previous pre boot loader during DDR initialization. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc:Add support of SPL non-relocationPrabhakar Kushwaha2014-04-22-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Current SPL code base has BSS section placed after reset_vector. This means they have to relocate to use the global variables. This put an implicit requirement of having SPL size = Memory/2. To avoid relocation: - Move bss_section within SPL range - Modify relocate_code() Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: Avoid hardcoding in SPL linker scriptPrabhakar Kushwaha2014-04-22-1/+6
| | | | | | | | | | | | | | | | | | | | SPL linker has fix location of bootpg and reset vector with respect to text base. It is not necessary to have fixed locations. Avoid such hardcoding. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: Move LAW_EN define outside of configPrabhakar Kushwaha2014-04-22-1/+2
| | | | | | | | | | | | | | | | | | | | | | LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence both are same. This cause compilation error. So LAW_EN define outside of configs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: Remove QE firmware copy from NANDPrabhakar Kushwaha2014-04-22-13/+0
| | | | | | | | | | | | | | | | | | | | qe_init() does not use data copied from NAND. Thise code is not tested or complied causing compilation error during NAND boot So, remove QE firmware copy from NAND to ddr. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | mpc85xx/t104x: Add deep sleep framework supportTang Yuantian2014-04-22-0/+24
| | | | | | | | | | | | | | | | | | | | When T104x soc wakes up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves before. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | mpc85xx: Add support for the supplement configuration unit registerTang Yuantian2014-04-22-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/cpu/mpc85xx: Add MAC address for layer 2 switchCodrin Ciubotariu2014-04-22-0/+29
| | | | | | | | | | | | | | | | | | | | | | T1040RDB and T1040QDS boards have an integrated l2 switch. The switch needs a MAC address for Layer 2 protocols (MSTP, LLDP, LACP, etc). Setting a MAC address on l2switchaddr will add a MAC in device-tree, under node l2switch. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Cc: York Sun <yorksun@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: Add workaround for erratum A007212York Sun2014-04-22-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun@freescale.com>
* | fsl/usb: Workaround for USB erratum-A007075Nikhil Badola2014-04-22-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | Put a delay of 5 millisecond after reset so that ULPI phy gets enough time to come out of reset. Erratum A007075 applies to following SOCs and their variants, if any P1010 rev 1.0 B4860 rev 1.0, 2.0 P4080 rev 2.0, 3.0 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | driver/ddr/fsl: Add DDR4 support to Freescale DDR driverYork Sun2014-04-22-3/+14
| | | | | | | | | | | | | | Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
* | powerpc/85xx: Fix e6500 L2 cache stash IDsScott Wood2014-04-22-4/+8
| | | | | | | | | | | | | | | | The value written to L2CSR1 didn't match the value written to the device tree. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | QE/U-QE: Add U-QE supportZhao Qiang2014-04-22-5/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and ↵Zhao Qiang2014-04-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T1040QDS and T1040RDBAneesh Bansal2014-04-22-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T2080QDSAneesh Bansal2014-04-22-1/+3
| | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for T2080QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: SECURE BOOT- Add secure boot target for T4240QDS and T4160QDSAneesh Bansal2014-04-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | Secure Boot Target is added for T4240QDS and T4160QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDSAneesh Bansal2014-04-22-6/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDSAneesh Bansal2014-04-22-7/+4
| | | | | | | | | | | | | | | | | | | | Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc8xxx: SECURE BOOT- Disable law 0 for non PBL platformsAneesh Bansal2014-04-22-0/+10
| | | | | | | | | | | | | | | | | | ISBC creates a LAW 0 entry for non PBL platforms, which is not disabled before transferring the control to uboot. The LAW 0 entry has to be disabled. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | PPC 85xx: Add qemu-ppce500 machineAlexander Graf2014-04-22-4/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For KVM we have a special PV machine type called "ppce500". This machine is inspired by the MPC8544DS board, but implements a lot less features than that one. It also provides more PCI slots and is supposed to be enumerated by device tree only. This patch adds support for the generic ppce500 machine and tries to rely solely on device tree for device enumeration. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | PPC 85xx: Add ELF entry pointAlexander Graf2014-04-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | We want to be able to directly execute the ELF binary without going through the u-boot.bin one. To know where we have to start executing this ELF binary we have to tell the linker where our entry point is. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | PPC: 85xx: Generalize DDR TLB mapping functionAlexander Graf2014-04-22-15/+40
| | | | | | | | | | | | | | | | | | | | The DDR mapping function really is just a generic virtual -> physical mapping function. Generalize it so it can support any virtual starting offset and IO maps just the same. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | PPC: 85xx: Remove IVOR resetAlexander Graf2014-04-22-76/+0
|/ | | | | | | | | | | There is no need to set IVORs to anything but their default values, so let's leave them where they are. Suggested-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> [York Sun: Add back $(obj)start.S section in mpc8572ds/Makefile] Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc: remove MOUSSE board supportMasahiro Yamada2014-04-18-88/+0
| | | | | | | | | | | Enough time has passed since this board was moved to Orphan. Remove. - Remove board/mousse/* - Remove include/configs/MOUSSE.h - Clean-up defined(CONFIG_MOUSSE) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: remove RPXClassic, RPXlite boards supportMasahiro Yamada2014-04-18-13/+1
| | | | | | | | | | | | | Enough time has passed since these boards were moved to Orphan. Remove. - Remove board/RPXlite/* - Remove board/RPXClassic/* - Remove include/configs/RPXlite.h - Remove include/configs/RPXClassic.h - Clean-up defined(CONFIG_RPXCLASSIC) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: remove ADS860, FADS823, FADS850SAR, FADS860T supportMasahiro Yamada2014-04-18-13/+1
| | | | | | | | | | | Enough time has passed since these boards were moved to Orphan. Remove. - Remove include/configs/{ADS860.h,FADS823.h,FADS850SAR.h,FADS860T.h} - Cleanup defined(CONFIG_ADS), defined(CONFIG_MPC823FADS), defined(CONFIG_MPC850SAR), defined(CONFIG_SYS_DAUGHTERBOARD) - Remove the entries from boards.cfg Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: remove MBX and MBX860T boards supportMasahiro Yamada2014-04-18-25/+0
| | | | | | | | | | | Enough time has passed since these boards were moved to Orphan. Remove. - Remove board/mbx8xx/* - Remove include/configs/{MBX.h,MBX860T.h} - Clean-up if defined(CONFIG_MBX) - Move the entries from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
generated by cgit v1.1 at 2024-11-27 01:41:53 +0000