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* kconfig: remove redundant "string" type in arch and board KconfigsMasahiro Yamada2014-09-13-12/+0
| | | | | | | | | | | | | | | | | | Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME} are specified in arch/Kconfig. We can delete the ones in arch and board Kconfig files. This commit can be easily reproduced by the following command: find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e ' /config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ { N s/\n[[:space:]]*string// } ' Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* net: Merge asm/fsl_enet.h into fsl_mdio.hClaudiu Manoil2014-09-08-24/+0
| | | | | | | | | | | | | | | fsl_enet.h defines the mapping of the usual MII management registers, which are included in the MDIO register block common to Freescale ethernet controllers. So it shouldn't depend on the CPU architecture but it should be actually part of the arch independent fsl_mdio.h. To remove the arch dependency, merge the content of asm/fsl_enet.h into fsl_mdio.h. Some files (like fm_eth.h) were simply including fsl_enet.h only for phy.h. These were updated to include phy.h instead. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
* mpc5xxx: Add stub implementation of cache functionsVasili Galka2014-09-02-0/+16
| | | | | | | | | | | | | Some drivers (e.g. net/e1000) reference these functions. So, this fixes the build of MVBC_P board. I'm not familiar with the MPC5xxx platform, maybe a full implementation shall be implemented instead of this stub in the future. Signed-off-by: Vasili Galka <vvv444@gmail.com> Cc: Wolfgang Denk <wd@denx.de>, Marek Vasut <marex@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* powerpc: mpc8xx: remove FLAGADM board supportMasahiro Yamada2014-08-21-4/+0
| | | | | | This board has been orphaned for a while and old enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc8xx: remove GEN860T, GEN806T_SC board supportMasahiro Yamada2014-08-21-4/+0
| | | | | | These boards have been orphaned for a while and old enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc8xx: remove SXNI855T board supportMasahiro Yamada2014-08-21-4/+0
| | | | | | This board has been orphaned for a while and old enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc8xx: remove svm_sc8xx boardMasahiro Yamada2014-08-21-8/+0
| | | | | | This board has been orphaned for a while and old enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc8xx: remove stxxtc board supportMasahiro Yamada2014-08-21-4/+0
| | | | | | This board has been orphaned for a while and old enough. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc/mpc85xx: Enabling CPC conditionally based on hwconfig optionsShaveta Leekha2014-08-20-2/+26
| | | | | | | | | | | If hwconfig does not contains "en_cpc" then by default all cpcs are enabled If this config is defined then only those individual cpcs which are defined in the subargument of "en_cpc" will be enabled e.g en_cpc:cpc1,cpc2; (this will enable cpc1 and cpc2) or en_cpc:cpc2; (this enables just cpc2) Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t104xrdb: support deep sleep in SPI/SD bootTang Yuantian2014-08-12-0/+15
| | | | | | | | | | | | Add deep sleep support in SPI/SD boot. The destination address second stage uboot image is loaded to is changed because currently this address will be used by kernel which means we can't reserve it for resume. Entry point to kernel is still placed in second stage uboot. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Make boot flag effectiveTang Yuantian2014-08-12-0/+2
| | | | | | | | | bootflag as a parameter is passed to board_init_f(). But it is not actually used in this function. Make it effective by assigned it to gd->flags. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-08-06-1/+17
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| * powerpc: mpc85xx watchdog init added to init_funcBoschung, Rainer2014-08-01-0/+3
| | | | | | | | | | | | | | | | | | | | | | When CONFIG_WATCHDOG is defined the board initialization just performs a WATCHDOG_RESET, an initialization of the watchdog is not done. This has been modified fot the MPC85xx, the board initialization calls its watchdog initialitzation allowing for full watchdog configuration very early in the boot phase. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: watchdog initialisation addedBoschung, Rainer2014-08-01-0/+8
| | | | | | | | | | | | | | | | Function to inititialize the cpu watchdog added. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> [York Sun: Add prototype in watchdog.h] Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc: macros for e500mc timer regs addedBoschung, Rainer2014-08-01-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For e500mc cores the watchdog timer period has to be set by means of a 6bit value, that defines the bit of the timebase counter used to signal a watchdog timer exception on its 0 to 1 transition. The macro used to set the watchdog period TCR_WP, was redefined for e500mc to support 6 WP setting. The parameter (x) given to the macro specifies the prescaling factor of the time base clock (fTB): watchdog_period = 1/fTB * 2^x Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: fix interrupt init to not affect watchdogBoschung, Rainer2014-08-01-1/+1
| | | | | | | | | | | | | | | | TCR watchdog bit are overwritten when dec interrupt is enabled. This has been fixed with this patch. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc: remove redundant CPU definitionMasahiro Yamada2014-07-30-12/+11
| | | | | | | | | | | | | | | | CONFIG_${CPU} is defined by Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Roese <sr@denx.de>
* | kconfig: delete redundant CONFIG_${ARCH} definitionMasahiro Yamada2014-07-30-1/+1
| | | | | | | | | | | | | | CONFIG_${ARCH} is defined by Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | kconfig: switch to KconfigMasahiro Yamada2014-07-30-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit enables Kconfig. Going forward, we use Kconfig for the board configuration. mkconfig will never be used. Nor will include/config.mk be generated. Kconfig must be adjusted for U-Boot because our situation is a little more complicated than Linux Kernel. We have to generate multiple boot images (Normal, SPL, TPL) from one source tree. Each image needs its own configuration input. Usage: Run "make <board>_defconfig" to do the board configuration. It will create the .config file and additionally spl/.config, tpl/.config if SPL, TPL is enabled, respectively. You can use "make config", "make menuconfig" etc. to create a new .config or modify the existing one. Use "make spl/config", "make spl/menuconfig" etc. for spl/.config and do likewise for tpl/.config file. The generic syntax of configuration targets for SPL, TPL is: <target_image>/<config_command> Here, <target_image> is either 'spl' or 'tpl' <config_command> is 'config', 'menuconfig', 'xconfig', etc. When the configuration is done, run "make". (Or "make <board>_defconfig all" will do the configuration and build in one time.) For futher information of how Kconfig works in U-Boot, please read the comment block of scripts/multiconfig.py. By the way, there is another item worth remarking here: coexistence of Kconfig and board herder files. Prior to Kconfig, we used C headers to define a set of configs. We expect a very long term to migrate from C headers to Kconfig. Two different infractructure must coexist in the interim. In our former configuration scheme, include/autoconf.mk was generated for use in makefiles. It is still generated under include/, spl/include/, tpl/include/ directory for the Normal, SPL, TPL image, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | kconfig: add board Kconfig and defconfig filesMasahiro Yamada2014-07-30-0/+1262
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds: - arch/${ARCH}/Kconfig provide a menu to select target boards - board/${VENDOR}/${BOARD}/Kconfig or board/${BOARD}/Kconfig set CONFIG macros to the appropriate values for each board - configs/${TARGET_BOARD}_defconfig default setting of each board (This commit was automatically generated by a conversion script based on boards.cfg) In Linux Kernel, defconfig files are located under arch/${ARCH}/configs/ directory. It works in Linux Kernel since ARCH is always given from the command line for cross compile. But in U-Boot, ARCH is not given from the command line. Which means we cannot know ARCH until the board configuration is done. That is why all the "*_defconfig" files should be gathered into a single directory ./configs/. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://www.denx.de/git/u-boot-ppc4xxTom Rini2014-07-28-2/+2
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| * | ppc: Make ppc4xx ready for CONFIG_SYS_GENERIC_BOARDDirk Eibach2014-07-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The generic board infrastructure assumes that gd is set by arch code. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-07-28-663/+158
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| * | mpc85xx/t104x: Enable L2 and CPC cache when resumeTang Yuantian2014-07-22-76/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When resume from deep sleep, uboot needs to enable L2 and CPC cache, or they would be keeping unusable in kernel because kernel didn't enble or initialized them. This patch didn't change the existing L2 cache enabling code, just put them in a function. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/chassis2: Configure and enable L2 cache for PPC clusters onlyShaveta Leekha2014-07-22-1/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t4240qds: fix offset of serdes when checking reference clockShaohui Xie2014-07-22-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | driver/ddr: Fix DDR4 driver for ARMYork Sun2014-07-22-0/+3
| | | | | | | | | | | | | | | | | | | | | Previously the driver was only tested on Power SoCs. Different barrier instructions are needed for ARM SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
| * | powerpc/mpc85xx: Removed support for G4060Sandeep Singh2014-07-22-2/+0
| | | | | | | | | | | | | | | | | | | | | G4060 has no PA cores, hence removing its support. Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | qe: move immap_qe.h from arch directory into common directoryZhao Qiang2014-07-22-584/+2
| | | | | | | | | | | | | | | | | | | | | | | | ls1021 is arm-core and supports qe too. Move immap_qe.h into common directory for both arm and powerpc. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/85xx: add fdt_fixup_dma3Shengzhou Liu2014-07-22-0/+47
| |/ | | | | | | | | | | | | | | On some SoC(e.g. T2080/T4240) the 3rd DMA is not functional if SRIO2 is chosen. we add fdt_fixup_dma3() to disable the 3rd DMA if SRIO2 is chosen. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | stdio: Pass device pointer to stdio methodsSimon Glass2014-07-23-8/+8
|/ | | | | | | | | | | | | | | | | | | | | | | | | | At present stdio device functions do not get any clue as to which stdio device is being acted on. Some implementations go to great lengths to work around this, such as defining a whole separate set of functions for each possible device. For driver model we need to associate a stdio_dev with a device. It doesn't seem possible to continue with this work-around approach. Instead, add a stdio_dev pointer to each of the stdio member functions. Note: The serial drivers have the same problem, but it is not strictly necessary to fix that to get driver model running. Also, if we convert serial over to driver model the problem will go away. Code size increases by 244 bytes for Thumb2 and 428 for PowerPC. 22: stdio: Pass device pointer to stdio methods arm: (for 2/2 boards) all +244.0 bss -4.0 text +248.0 powerpc: (for 1/1 boards) all +428.0 text +428.0 Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
* blackfin, powerpc: remove redundant definitions of ARRAY_SIZEMasahiro Yamada2014-07-07-2/+0
| | | | | | | | | Since ARRAY_SIZE macro is defined in include/common.h, re-defining it in arch-specific files is redundant. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Sonic Zhang <sonic.zhang@analog.com>
* mpc8xx: remove spc1920 board supportMasahiro Yamada2014-07-07-1/+0
| | | | | | This board is old enough and has no maintainer. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* mpc8xx: remove fads board supportMasahiro Yamada2014-07-07-112/+2
| | | | | | These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* mpc8xx: remove netta, netta2, netphone board supportMasahiro Yamada2014-07-07-20/+0
| | | | | | These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* mpc8xx: remove RPXlite_dw, quantum board supportMasahiro Yamada2014-07-07-14/+0
| | | | | | These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* mpc8xx: remove qs850, qs860t board supportMasahiro Yamada2014-07-07-10/+0
| | | | | | These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-06-05-6/+469
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| * powerpc/mpc85xx: Add workaround to enable TDM on T1040Sandeep Singh2014-06-05-1/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/serdes: Add the workaround for erratum A-007186Shaveta Leekha2014-06-05-2/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Add workaround for DDR erratum A004508York Sun2014-06-05-0/+21
| | | | | | | | | | | | | | | | | | | | | | When the DDR controller is initialized below a junction temperature of 0°C and then operated above a junction temperature of 65°C, the DDR controller may cause receive data errors, resulting ECC errors and/or corrupted data. This erratum applies to the following SoCs and their variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023, P2020. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/t2080: add serdes2 protocol 0x27Shengzhou Liu2014-06-05-0/+1
| | | | | | | | | | | | | | Add a new serdes2 protocol 0x27. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/t4qds: Add alternate serdes protocols to align with A-007186Shaohui Xie2014-06-05-0/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to increase and cause the PLL to unlock when the temperature delta from the time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC VCO. Only the protocols using Ring VCOs are impacted. Workaround: For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need to use alternate serdes protocols. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * board/t208x: update t2080qds/t2080rdb for errata A-007186Shengzhou Liu2014-06-05-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | As errata A-007186, we need to use the alternate serdes protocol instead of those impacted protocols. - add support for serdes protocols: 0x1b, 0x50, 0x5e, 0x64, 0x6a, 0xd2, 0x67, 0x70. - update t2080_rcw.cfg to adapt to new rcw_66_15 for t2080qds and t2080rdb. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | nand_spl: remove nand_spl infrastructureMasahiro Yamada2014-06-05-3/+0
|/ | | | | | | Remove the common infrastructure of nand_spl and clean-up the code inside ifdef(CONFIG_NAND_U_BOOT)..endif. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: hiddendragon: remove orphan boardMasahiro Yamada2014-05-30-12/+0
| | | | | | | | | | | This board has been orphan for a while. (Emails to its maintainer have been bouncing.) Because MPC82xx family is old enough, nobody would pick up the maintainership on it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denx <wd@denx.de>
* powerpc: mpc8260ads: remove orphan boardMasahiro Yamada2014-05-30-15/+0
| | | | | | | | | | | This board has been orphan for a while. (Emails to its maintainer have been bouncing.) Because MPC82xx family is old enough, nobody would pick up the maintainership on it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denx <wd@denx.de>
* m68k: powerpc: Clean up do_mdm_initSimon Glass2014-05-29-8/+0
| | | | | | | | This code seems unnecessarily complex. We really just need to check the global_data. Now that is it all in one place, and not arch-specific, this is pretty easy. Signed-off-by: Simon Glass <sjg@chromium.org>
* mpc85xx/p1020:Define number of USB controllers used on P1020RDB-PD platformramneek mehresh2014-05-16-0/+2
| | | | | | | | P1020 SoC which has two USB controllers, but only first one is used on this platform. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Added B4460 supportShaveta Leekha2014-05-16-0/+2
| | | | | | | | | | | B4460 differs from B4860 only in number of CPU cores, hence used existing support for B4860. B4460 has 2 PPC cores whereas B4860 has 4 PPC cores. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-12-23 10:06:41 +0000