summaryrefslogtreecommitdiff
path: root/arch/powerpc
Commit message (Collapse)AuthorAgeLines
* env: Use getenv_yesno() more generallyJoe Hershberger2012-12-13-10/+3
| | | | | | | Move the getenv_yesno() to env_common.c and change most checks for 'y' or 'n' to use this helper. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* Add strcasecmp() and strncasecmp()Simon Glass2012-12-11-1/+1
| | | | | | | | | | | strncasecmp() is present as strnicmp() but disabled. Make it available and define strcasecmp() also. There is a only a small performance penalty to having strcasecmp() call strncasecmp(), so do this instead of a standalone function, to save code space. Update the prototype in arch-specific headers as needed to avoid warnings. Signed-off-by: Simon Glass <sjg@chromium.org>
* mpc5200: Add SPL supportStefan Roese2012-12-05-0/+201
| | | | | | | This patch adds SPL booting support (NOR flash) for the MPC5200 platforms. Signed-off-by: Stefan Roese <sr@denx.de>
* SPL: Port SPL framework to powerpcStefan Roese2012-12-05-0/+46
| | | | | | | | | | | | | This patch enables the SPL framework to be used on powerpc platforms and not only ARM. timer_init() does not exist on PPC systems. The timer (decrementer) is initialized and enabled in interrupt_init() here. And currently interrupt_init() is called after relocation to SDRAM. Since the only powerpc SPL implementation (a3m071) doesn't need a timer, let's remove this timer_init() call for PPC systems. Signed-off-by: Stefan Roese <sr@denx.de>
* powerpc: Extract EPAPR_MAGIC constants into processor.hStefan Roese2012-12-05-7/+6
| | | | | | | | By extracting these defines into a header, they can be re-used by other C sources as well. This will be done by the SPL framework OS boot support. Signed-off-by: Stefan Roese <sr@denx.de>
* powerpc/mpc85xx: Fix a bug introduced by CONFIG_PPC_SPINTABLE_COMPATIBLEYork Sun2012-11-27-2/+2
| | | | | | | | | | | Fix a bug introduced by this patch powerpc/mpc85xx: Temporary fix for spin table backward compatibility Should have checked both CONFIG_PPC_SPINTABLE_COMPATIBLE and CONFIG_MP in cpu_init.c. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: update the work-around for P4080 erratum SERDES-9Timur Tabi2012-11-27-7/+16
| | | | | | | | | | The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p4080ds: fix PCI-e x8 link training down failureYuanquan Chen2012-11-27-0/+4
| | | | | | | | | | | | Due to SerDes configuration error, if we set the PCI-e controller link width as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to PCI-e slot, it fails to train down to the PCI-e device's link width. According to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between RC and EP. Signed-off-by: Yuanquan Chen <B41889@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/corenet_ds: move SATA config to board configurationZang Roy-R619112012-11-27-7/+0
| | | | | | | | | | | | | | | | | | | | board configuration file is included before asm/config_mpc85xx.h. however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h. it will never take effective in the board configuration file for this kind of code : #ifdef CONFIG_FSL_SATA_V2 ... #endif To solve this problem, move CONFIG_FSL_SATA_V2 to board configuration header file. This patch reverts Timur's commit:3e0529f742e893653848494ffb9f7cd0d91304bf Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: implement check for erratum A-004580 work-aroundTimur Tabi2012-11-27-1/+50
| | | | | | | | | | | | | | | | | | | The work-around for erratum A-004580 ("Internal tracking loop can falsely lock causing unrecoverable bit errors") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004580, we can do this by verifying that the values in the specific registers that the work-around says to update. This change requires access to the SerDes lane sub-structure in serdes_corenet_t, so we make it a named struct. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8xxx: take fdt_fixup_crypto_node() off the checkstack listKim Phillips2012-11-27-3/+3
| | | | | | | | | by moving compat_strlist into the .bss section. 0xfe004d80 fdt_fixup_crypto_node [u-boot]: 264 Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Temporary fix for spin table backward compatibilityYork Sun2012-11-27-1/+52
| | | | | | | | | | | | Once u-boot sets the spin table to cache-enabled memory, old kernel which uses cache-inhibit mapping without coherence will not work properly. We use this temporary fix until kernel has updated its spin table code. For now this fix is activated by default. To disable this fix for new kernel, set environmental variable "spin_table_compat=no". After kernel has updated spin table code, this default shall be changed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: implement check for erratum A-004849 work-aroundTimur Tabi2012-11-27-0/+66
| | | | | | | | | | | | | | | | The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a deadlock under certain traffic patterns causing the system to hang") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004849, we can do this by verifying that the values in the specific registers that the work-around says to update. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx/p5040: add CONFIG_SYS_PPC64, del CONFIG_SYS_FSL_ELBC_MULTIBIT_ECCTimur Tabi2012-11-27-1/+1
| | | | | | | | | | | | The P5040 has an e5500 core, so CONFIG_SYS_PPC64 should be defined in config_mpc85xx.h. This macro was absent in the initial P5040 patch because it crossed paths with the patch that introduced the macro. Also delete CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC, since it's not used in the upstream U-Boot. It's a holdover from the SDK. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 8xxx: Change all 8*xx_DDR addresses to 8xxxAndy Fleming2012-11-27-61/+44
| | | | | | | | | | | | | | | | | | | | | | There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2012-11-26-82/+573
|\
| * spl/85xx: new SPL supportScott Wood2012-11-26-9/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL and CONFIG_SPL_BUILD, respectively. CONFIG_NAND_SPL can be removed once the last mpc85xx nand_spl target is gone. CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't seem right to overload it for meaning SPL as well as nand_spl does. Even if it's somewhat appropriate for the main u-boot, the SPL itself isn't (necessarily) ramboot, and we don't have separate configs for SPL and main u-boot. It was also inconsistent, as other platforms such as mpc83xx didn't use CONFIG_RAMBOOT in this way. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * spl/powerpc: introduce CONFIG_SPL_INIT_MINIMALScott Wood2012-11-26-15/+70
| | | | | | | | | | | | | | | | | | cpu_init_nand.c is renamed to spl_minimal.c as it is not really NAND-specific. Signed-off-by: Scott Wood <scottwood@freescale.com> --- v2: factor out START, and change cpu_init_nand.c to spl_minimal.c Cc: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: consistently use COBJS-yScott Wood2012-11-26-9/+10
| | | | | | | | | | | | | | | | A subsequent patch will conditionalize some of the files that are currently unconditional. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.cScott Wood2012-11-26-0/+0
| | | | | | | | | | | | | | There is nothing really NAND-specific about this file. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * spl/mpc85xx: move udelay to cpu codeScott Wood2012-11-26-0/+17
| | | | | | | | | | | | | | | | | | It applies to non-Freescale 85xx boards as well as Freescale boards, so it doesn't belong in board/freescale. Plus, it needs to come out of nand_spl if it's to be used by the new SPL. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxxScott Wood2012-11-26-0/+334
| | | | | | | | | | | | | | | | | | | | | | It's arch code and not a driver, so move it where it belongs. When it originally went into drivers/misc there was no 8xxx CPU directory. This will make new-SPL support a little easier since we can keep the CPU stuff together and not need to pull stuff in from drivers/misc. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: fix TLB alignmentScott Wood2012-11-26-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the RAMBOOT/SPL case we were creating a TLB entry starting at CONFIG_SYS_MONITOR_BASE, and just hoping that the base was properly aligned for the TLB entry size. This turned out to not be the case with NAND SPL because the main U-Boot starts at an offset into the image in order to skip the SPL itself. Fix the TLB entry to always start at a proper alignment. We still assume that CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary thus requiring multiple TLB entries. Signed-off-by: Scott Wood <scottwood@frescale.com> Cc: Andy Fleming <afleming@freescale.com>
| * powerpc: change .fixup test to a GCC version testScott Wood2012-11-26-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was introduced by commit 244615197469dd6fe75ae082f38424b97c79aeaf, but it fails in a minimal SPL build where the only thing in arch/powerpc/lib is cache.c, which apparently doesn't generate any fixup records. The problem is reported to occur with GCC 3.x, so insist on GCC 4.0 or newer. Patterned after checkthumb as suggested by Tom Rini. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Tom Rini <trini@ti.com> -- v2: test gcc version instead of testing nothing
| * powerpc/mpc85xx: add comma before "already enabled"Scott Wood2012-11-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Now outputs like this: L2: 512 KB already enabled, moving to 0xf8f80000 rather than this: L2: 512 KB already enabledmoving to 0xf8f80000 Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@gmail.com>
| * powerpc/mpc85xx: move debug tlb entry after TLB is in known stateScott Wood2012-11-26-44/+40
| | | | | | | | | | | | | | | | | | | | | | | | Previously, in many if not all configs we were creating overlapping TLB entries which is illegal. This caused a crash during boot when moving p2020rdb NAND SPL into L2 SRAM. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Andy Fleming <afleming@freescale.com> -- Prabhakar, please test that debug still works.
* | usb: use linux/usb/ch9.h instead of usbdescriptors.hIlya Yanok2012-11-20-2/+2
|/ | | | | | | | | | | | | | | | | | | | | | Linux usb/ch9.h seems to have all the same information (and more) as usbdescriptors.h so use the former instead of the later one. As a consequense of this change USB_SPEED_* values don't correspond directly to EHCI speed encoding anymore, I've added necessary recoding in EHCI driver. Also there is no point to put speed into pipe anymore so it's removed and a bunch of host drivers fixed to look at usb_device->speed instead. Old usbdescriptors.h included is not removed as it seems to be used by old USB device code. This makes usb.h and usbdevice.h incompatible. Fortunately the only place that tries to include both are the old MUSB code and it needs usb.h only for USB_DMA_MINALIGN used in aligned attribute on musb_regs structure but this attribute seems to be unneeded (old MUSB code doesn't support any DMA at all). Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* powerpc/mpc83xx: sparse fixesKim Phillips2012-11-04-4/+6
| | | | | | | | | | | | | | | | | | | | | fdt.c:91:78: warning: Using plain integer as NULL pointer fdt.c:103:78: warning: Using plain integer as NULL pointer speed.c:55:11: warning: symbol 'corecnf_tab' was not declared. Should it be static? speed.c:519:5: warning: symbol 'do_clocks' was not declared. Should it be static? mpc8313erdb.c:73:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:74:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:75:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:76:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:79:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:80:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:81:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:82:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:85:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:86:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:87:17: warning: obsolete struct initializer, use C99 syntax mpc8313erdb.c:88:17: warning: obsolete struct initializer, use C99 syntax Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* powerpc/mpc85xx: sparse fixesKim Phillips2012-11-04-2/+2
| | | | | | | | | | | | | | | | | fsl_corenet_serdes.c:485:6: warning: symbol '__soc_serdes_init' was not declared. Should it be static? cpu_init.c:185:6: warning: symbol 'invalidate_cpc' was not declared. Should it be static? bcsr.c:28:27: warning: non-ANSI function declaration of function 'enable_8568mds_duart' bcsr.c:39:33: warning: non-ANSI function declaration of function 'enable_8568mds_flash_write' bcsr.c:46:34: warning: non-ANSI function declaration of function 'disable_8568mds_flash_write' bcsr.c:53:29: warning: non-ANSI function declaration of function 'enable_8568mds_qe_mdio' bcsr.c:28:33: warning: non-ANSI function declaration of function 'enable_8569mds_flash_write' bcsr.c:33:34: warning: non-ANSI function declaration of function 'disable_8569mds_flash_write' bcsr.c:38:28: warning: non-ANSI function declaration of function 'enable_8569mds_qe_uec' bcsr.c:63:47: warning: non-ANSI function declaration of function 'disable_8569mds_brd_eeprom_write_protect' ngpixis.c:245:1: error: directive in argument list ngpixis.c:247:1: error: directive in argument list Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* arch/powerpc/cpu/mpc8xxx/: sparse fixesKim Phillips2012-11-04-7/+10
| | | | | | | | | | | | | | | | | | | | | ctrl_regs.c:31:5: warning: symbol 'fsl_ddr_get_version' was not declared. Should it be static? cpu.c:135:14: warning: non-ANSI function declaration of function 'cpu_mask' cpu.c:154:18: warning: non-ANSI function declaration of function 'cpu_numcores' cpu.c:37:17: warning: symbol 'cpu_type_list' was not declared. Should it be static? cpu.c:117:17: warning: symbol 'cpu_type_unknown' was not declared. Should it be static? fsl_lbc.c:14:6: warning: symbol '__lbc_sdram_init' was not declared. Should it be static? and: lc_common_dimm_params.c:15:1: warning: symbol 'compute_cas_latency_ddr3' was not declared. Should it be static? making it static produces the following compiler warning: lc_common_dimm_params.c:15:1: warning: 'compute_cas_latency_ddr3' defined but not used [-Wunused-function] so we protect it with the preprocessor. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* arch/powerpc/lib/board.c, *traps.c: sparse fixesKim Phillips2012-11-04-303/+206
| | | | | | | | | | | | | traps.c:*:1: warning: symbol 'print_backtrace' was not declared. Should it be static? traps.c:93:1: warning: symbol '_exception' was not declared. Should it be static? board.c:166:6: warning: symbol '__board_add_ram_info' was not declared. Should it be static? board.c:174:5: warning: symbol '__board_flash_wp_on' was not declared. Should it be static? board.c:187:6: warning: symbol '__cpu_secondary_init_r' was not declared. Should it be static? board.c:265:12: warning: symbol 'init_sequence' was not declared. Should it be static? board.c:348:5: warning: symbol '__fixup_cpu' was not declared. Should it be static? board.c:405:53: warning: Using plain integer as NULL pointer Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* arch/powerpc/lib/extable.c: sparse fixKim Phillips2012-11-04-4/+1
| | | | | | | | | | | | extable.c:66:9: warning: symbol 'ex_tab_message' was not declared. Should it be static? making it static can produce a new build warning on some boards: extable.c:66:12: warning: 'ex_tab_message' defined but not used [-Wunused-variable] but ex_tab_message doesn't do much even when used, so just remove it. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* arch/powerpc/include/asm/io.h: fix warning: preprocessor token __iomem redefinedKim Phillips2012-11-04-1/+0
| | | | | | | | | | | | a fixup __iomem definition in arch code appears to be placed there as a cover up from a code import from linux when u-boot didn't yet have a compiler.h, introduced by commit 812711ce6b3a386125dcf0d6a59588e461abbb87 "Implement __raw_{read,write}[bwl] on all architectures". git show 812711ce6b3a386125dcf0d6a59588e461abbb87:include/linux/compiler.h fatal: Path 'include/linux/compiler.h' exists on disk, but not in '812711ce6b3a386125dcf0d6a59588e461abbb87'. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* include/linux/byteorder: import latest endian definitions from linuxKim Phillips2012-11-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | u-boot's byteorder headers did not contain endianness attributions for use with sparse, causing a lot of false positives. Import the kernel's latest definitions, and enable them by including compiler.h and types.h. They come with 'const' added for some swab functions, so fix those up, too: include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default] Also, note: u-boot's historic __BYTE_ORDER definition has been preserved (for the time being at least). We also remove ad-hoc barrier() definitions, since we're including compiler.h in files that hadn't in the past: macb.c:54:0: warning: "barrier" redefined [enabled by default] In addition, including compiler.h in byteorder changes the 'noinline' definition to expand to __attribute__((noinline)). This fixes arch/powerpc/lib/bootm.c: bootm.c:329:16: error: attribute '__attribute__': unknown attribute bootm.c:329:16: error: expected ')' before '__attribute__' bootm.c:329:25: error: expected identifier or '(' before ')' token powerpc sparse builds yield: include/common.h:356:22: error: marked inline, but without a definition the unknown-reason inlining without a definition is considered obsolete given it was part of the 2002 initial commit, and no arm version was 'fixed.' also fixed: ydirectenv.h:60:0: warning: "inline" redefined [enabled by default] and: Configuring for devconcenter - Board: intip, Options: DEVCONCENTER make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1 make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2 powerpc-fsl-linux-size: './u-boot': No such file 4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration': include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available 4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here and: In file included from crc32.c:50:0: crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration] crc32table.h:4:1: error: initializer element is not constant crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]') Signed-off-by: Kim Phillips <kim.phillips@freescale.com> [trini: Remove '#endif' in include/common.h around setenv portion] Signed-off-by: Tom Rini <trini@ti.com>
* PPC: remove dead boards (AMX860, c2mon, ETX094, IAD210, LANTEC, SCM)Wolfgang Denk2012-10-28-16/+2
| | | | | | | | | These boards have long reached EOL, and there has been no indication of any active users of such hardware for years. Get rid of the dead weight. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Wolfgang Grandegger <wg@denx.de>
* mpc83xx: add support for mpc8309Gerlando Falauto2012-10-23-1/+84
| | | | | | | | | This processor, though very similar to other members of the PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides yet another feature set than any supported sibling. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* cleanup: introduce CONFIG_MPC830xGerlando Falauto2012-10-23-2/+5
| | | | | | | | | Introduce a new configuration token CONFIG_MPC830x to be shared among mpc8308 and mpc8309. Define it for existing 8308 boards, and refactor existing common code so to make future introduction of 8309 simpler. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* cleanup: use CONFIG_QE instead of CONFIG_MPC8360 || CONFIG_MPC832xGerlando Falauto2012-10-23-4/+4
| | | | | | | | | simplify #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) for qe variables with #if defined(CONFIG_QE) Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2012-10-22-464/+3412
|\
| * 85xx: Protect timeout_save variable with ifdefsAndy Fleming2012-10-22-1/+4
| | | | | | | | | | | | | | | | The timeout_save variable was only used by the DDR111_134 erratum code. It was being set, but never used. Newer compilers will actually complain about this. Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/boot: Change the compile macro for SRIO & PCIE boot master moduleLiu Gang2012-10-22-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the SRIO and PCIE boot master module will be compiled into the u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this macro has been included by all the corenet architecture platform boards. But in fact, it's uncertain whether all corenet platform boards support this feature. So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add a special macro for every board which can support the feature. This special macro will be defined in the header file "arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO and PCIE boot master module should be compiled into the board u-boot image. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * poweprc/85xx: add QMan frequency info and fdt fixup.Haiying Wang2012-10-22-0/+13
| | | | | | | | | | | | | | | | Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel driver can use it to calculate the shaper prescaler and rate. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * mpc85xx/portals: Add qman and bman ip_cfg field into portal infoHaiying Wang2012-10-22-2/+11
| | | | | | | | | | | | | | | | | | Because QMan3.0 and BMan2.1 used ip_cfg in ip_rev_2 register to differ the total portal number, buffer pool number etc, we can use this info to limit those resources in kernel driver. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platformYork Sun2012-10-22-10/+20
| | | | | | | | | | | | | | | | | | New corenet platforms with chassis2 have separated DDR clock inputs. Use CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of detecting and displaying synchronous vs asynchronous mode. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1York Sun2012-10-22-112/+151
| | | | | | | | | | | | | | | | | | | | | | | | Move spin table to cached memory to comply with ePAPR v1.1. Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. 'M' bit is set for DDR TLB to maintain cache coherence. See details in doc/README.mpc85xx-spin-table. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Remove R6 from spin tableYork Sun2012-10-22-6/+4
| | | | | | | | | | | | | | | | R6 was in ePAPR draft version but was dropped in official spec. Removing it to comply. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Fix DDR SPD failed messageYork Sun2012-10-22-1/+13
| | | | | | | | | | | | | | | | Since empty DIMM slot is allowed on other than the first slot, remove the error message if SPD is not found in this case. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Add auto select bank interleaving modeYork Sun2012-10-22-1/+32
| | | | | | | | | | | | | | | | | | | | | | Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or cs0_cs1 interleaving, or non-interleaving if not available. Fix the message of interleaving disabled if controller interleaving is enabled but DIMMs don't support it. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Add workaround for DDR erratum A004934York Sun2012-10-22-0/+7
| | | | | | | | | | | | | | | | | | After DDR controller is enabled, it performs a calibration for the transmit data vs DQS paths. During this calibration, the DDR controller may make an inaccurate calculation, resulting in a non-optimal tap point. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: software workaround for DDR erratum A-004468York Sun2012-10-22-18/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot space translation utilizes the pre-translation address to select the DDR controller target. However, the post-translation address will be presented to the selected DDR controller. It is possible that the pre- translation address selects one DDR controller but the post-translation address exists in a different DDR controller when using certain DDR controller interleaving modes. The device may fail to boot under these circumstances. Note that a DDR MSE error will not be detected since DDR controller bounds registers are programmed to be the same when configured for DDR controller interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit v1.1 at 2024-12-23 21:35:58 +0000