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* powerpc: fix 8xx and 82xx type-punning warnings with GCC 4.7Scott Wood2013-06-11-21/+35
| | | | | | | | | | | C99's strict aliasing rules are insane to use in low-level code such as a bootloader, but as Wolfgang has rejected -fno-strict-aliasing in the past, add a union so that 16-bit accesses can be performed. Compile-tested only. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-30-6351/+755
|\ | | | | | | | | | | Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
| * powerpc/mpc85xx: Clear L1 D-cache lockYork Sun2013-05-24-0/+1
| | | | | | | | | | | | | | | | dcbi instruction has been used to clear D-cache lock. However, the cache lock is persistent for e6500 core. Use dcblc to clear the lock explicitly. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * SECURE BOOT - Removed deletion of TLB entries codeRuchika Gupta2013-05-24-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Acked-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/b4860qds: Add LAW Target ID and Create LAW entry for MapleShaveta Leekha2013-05-24-0/+2
| | | | | | | | | | Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/B4: Merge B4420 and B4860 in config_mpc85xx.hPoonam Aggrwal2013-05-24-23/+11
| | | | | | | | | | | | | | | | | | | | | | | | B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify the defines. - Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere. - defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G. Also move CONFIG_E6500 out of B4860QDSds.h into config_mpc85xx.h. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Allow DDR overclockYork Sun2013-05-24-2/+0
| | | | | | | | | | | | | | | | | | | | Allow DDR clock runs faster than SPD specifes. This may cause memory failure, but the user should know what is going to happen when using higher than expected DDR clock. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/chassis2: Change core numbering schemeYork Sun2013-05-24-58/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Add T1040 and variant SoCsYork Sun2013-05-24-0/+282
| | | | | | | | | | | | | | | | | | T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/T4160: Merge T4160 and T4240 in config_mpc85xx.hYork Sun2013-05-24-32/+10
| | | | | | | | | | | | | | | | T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Add e6500 L2 replacement policy selectionJames Yang2013-05-24-1/+11
| | | | | | | | | | | | | | This is compile-time config. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: check if core is disabled for showing statusYork Sun2013-05-24-0/+2
| | | | | | | | | | | | | | | | "cpu <num> status" should check if core is disabled before printing the spin table location. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Enable L2 cache parity/ECC error checkingJames Yang2013-05-24-2/+2
| | | | | | | | | | Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2013-05-15-107/+376
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| | * powerpc/mpc8xxx: Allow board file to override DDR address assignmentYork Sun2013-05-14-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This gives boards flexibility to assign other than default addresses to each DDR controller. For example, DDR controler 2 can have 0 as the base and DDR controller 1 has higher memory. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Update workaround for DDR erratum A-004934York Sun2013-05-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The workaround has been updated to use a slightly different magic number. Change from 0x00003000 to 0x30003000. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.cRoy Zang2013-05-14-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY initialization can be reused in kernel without “usb start” command. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/85xx: fix build error introduced by serdes_get_prtclShengzhou Liu2013-05-14-1/+0
| | | | | | | | | | | | | | | | | | | | | Removed unused declare serdes_get_prtcl() which was no longer needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * t4240qds/eth: fixup ethernet for t4240qdsShengzhou Liu2013-05-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1, Implemented board_ft_fman_fixup_port() to fix port for kernel. 2, Implemented fdt_fixup_board_enet() to fix node status of different slots and interfaces. 3, Adding detection of slot present for XGMII interface. 4, There is no PHY for XFI, so removed related phy address settings. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/85xx: add missing QMAN frequency calculationShaohui Xie2013-05-14-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not be initialized, and QMAN will have a wrong frequency display. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Add T4160 SoCYork Sun2013-05-14-2/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/t4240: Fix SerDes protocol arrays with const prefixYork Sun2013-05-14-7/+7
| | | | | | | | | | | | | | | | | | | | | Protocols are constants. Fix arrays with const prefix. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Fix PIR parsing for chassis2York Sun2013-05-14-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | The PIR parsing algorithm we used is not only for E6500. It applies to all SoCs with chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/corenet2: Print SerDes protocol in decimalYork Sun2013-05-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use decimal and hexadecimal for protocol numbers. It helps to match with SoC user manual. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * T4/USB: Add USB 2.0 UTMI dual phy supportRoy Zang2013-05-14-2/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Fix portal setupYork Sun2013-05-14-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Missing nodes of crypto, pme, etc in device tree is not a fatal error. Setting up the qman portal should skip the missing node and continue to finish the rest. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc8xxx: Fix DDR 3-way interleavingYork Sun2013-05-14-8/+11
| | | | | | | | | | | | | | | | | | | | | Should check if interleaving is enabled before using interleaving mode. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * T4/SerDes: correct the SATA indexRoy Zang2013-05-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Lane H on SerDes4 should be SATA2 instead of SATA1 Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * e6500: Move L1 enablement after L2 enablementAndy Fleming2013-05-14-47/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The L1 D-cache on e6500 is write-through. This means that it's not considered a good idea to have the L1 up and running if the L2 is disabled. We don't actually *use* the L1 until after the L2 is brought up on e6500, so go ahead and move the L1 enablement after that code is done. Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Update corenet global utility block registersYork Sun2013-05-14-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Add definitions for HDBCR registersAndy Fleming2013-05-14-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | Makes it a bit easier to see if we've properly set them. While we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually use those definitions. Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/B4860: Corrected FMAN1 operating frequency print at u-bootSandeep Singh2013-05-14-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | The bit positions for FMAN1 freq in RCW is different for B4860. Also addded a case when FMAN1 frewuency is equal to systembus. Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Power: remove support for Freescale MPC8220Wolfgang Denk2013-05-15-6061/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale MPC8220 Power Architecture processors have long reached EOL; Freescale does not even list these any more on their web site. Remove the code to avoid wasting maitaining efforts on dead stuff. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andy Fleming <afleming@gmail.com>
| * | powerpc: Use image_setup_linux() instead of local codeSimon Glass2013-05-14-83/+1
| |/ | | | | | | | | | | | | Rather than having similar code in powerpc, use image_setup_linux() which should be common across all architectures that use the FDT. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-396/+3
|\ \ | |/ |/| | | | | | | Conflicts: drivers/mtd/nand/mxc_nand_spl.c include/configs/m28evk.h
| * mpc: iim: Switch to common fsl_iimBenoît Thébaudeau2013-04-28-396/+1
| | | | | | | | | | | | | | Make all mpc512x code point to the new common fsl_iim driver, and remove the former mpc512x-specific iim driver. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * Add fsl_iim driverBenoît Thébaudeau2013-04-28-0/+2
| | | | | | | | | | | | Add a fsl_iim driver common to i.MX and MPC. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-05-02-45/+109
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| * | powerpc/mpc85xx: Changed LIODN offset valuesCristian Sovaiala2013-05-02-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extending LIODN offset range from 1-5 to 1-10 While using a qman portal with a higher index the LIODN offset is incorrectly set, thus extending the range of offsets covers all 10 qman portals Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Acked-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/mpc85xx: Extend workaround for erratum DDR_A003 to other SoCsYork Sun2013-05-02-0/+3
| | | | | | | | | | | | | | | | | | | | | Erratum DDR_A003 applies to P5020, P3041, P4080, P3060, P2041, P5040. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/85xx: add SerDes bank 4 lanesTimur Tabi2013-05-02-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Only some chips have four SerDes banks, so don't define lanes for a bank that doesn't exist. Signed-off-by: Timur Tabi <timur@tabi.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/mpc85xx:IFC Errata A003399 is not valid for BSC913xPrabhakar Kushwaha2013-05-02-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | As per Errata list of BSC9131 and BSC9132, IFC Errata A003399 is no more valid. So donot compile its workaround. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | mpc85xx: Fix a compiler warning when CONFIG_WATCHDOG is turned onHorst Kronstorfer2013-05-02-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | cpu.c:288:2: warning: implicit declaration of function 'reset_85xx_watchdog' [-Wimplicit-function-declaration] Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0)Xulei2013-05-02-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | fman/mEMAC: set SETSP bit in IF_MODE regisgter for RGMII speedZang Roy-R619112013-05-02-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some legacy RGMII phys don't have in band signaling for the speed information. so set the RGMII MAC mode according to the speed got from PHY. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Reported-by: John Traill <john.traill@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/mpc85xx: set clock-frequency for T4/B4 clockgen nodeTang Yuantian2013-05-02-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | For T4/B4, the clockgen node compatible string is updated to version 2. Add clock-frequency setting for this new version. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/b4860: Adding workaround errata A-005871Shengzhou Liu2013-05-02-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Per the latest errata updated, B4860/B4420 Rev 1.0 has also errata A-005871, so adding define A-005871 for B4 SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/b4: Fix the wrong register offset of B4 PCIE moduleLiu Gang2013-05-02-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4420/B4860 PCIE can not work because of the wrong definition of the PCIE register offset in the file: arch/powerpc/include/asm/immap_85xx.h Add the judgement of B4420/B4860 to make the register offset to: #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/mpc85xx: add setting of clock-frequency for mpic nodeDongsheng.wang@freescale.com2013-05-02-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Set the device tree property associated with the mpic source frequency. The frequency is used for mpic timer. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/mpc85xx: Add revision properties in portal device tree node 'pme'Jeffrey Ladouceur2013-05-02-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'fsl,pme-rev1' and 'fsl-pme-rev2' properties have been added to the pme portal node. This is required for software to determine which version of PME hardware is present and take appropriate actions. These properties are a direct reflection of the corresponding ccsr pme register value. Also removed unnecessary static global variables. Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit v1.1 at 2024-12-29 15:57:18 +0000