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* Merge branch 'next' of git://git.denx.de/u-bootWolfgang Denk2012-07-30-1/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://git.denx.de/u-boot: MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c doc: cleanup - move board READMEs into respective board directories net: sh_eth: add support for SH7757's GETHER net: sh_eth: modify the definitions of regsiter net: sh_eth: add SH_ETH_TYPE_ condition net: sh_eth: clean up for the SH7757's code net: fec_mxc: Fix MDC for xMII net: fec_mxc: Fix setting of RCR for xMII net: nfs: make NFS_TIMEOUT configurable net: Inline the new eth_setenv_enetaddr_by_index function net: allow setting env enetaddr from net device setting net/designware: Consecutive writes to the same register to be avoided CACHE: net: asix: Fix asix driver to work with data cache on net: phy: micrel: make ksz9021 phy accessible net: abort network initialization if the PHY driver fails phylib: phy_startup() should return an error code on failure net: tftp: fix type of block arg to store_block Signed-off-by: Wolfgang Denk <wd@denx.de>
| * MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.cMarek Vasut2012-07-30-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpu.c: In function ‘check_CPU’: cpu.c:256:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Subject slightly changed. Signed-off-by: Wolfgang Denk <wd@denx.de> Tested on TQM855MDCBAB7-T66.102 (MPC855T at 66 MHz) and TQM860LDB0A3-T50.202 (MPC860T at 50MHz). Tested-by: Wolfgang Denk <wd@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* | MPC83xx, MPC85xx: compile stub cache functionStefano Babic2012-07-21-2/+2
|/ | | | | | | | | | | | | | | | | An empty flush_dcache_range() was added into MPC83xx and MPC85xx to work with drivers shared with other architecture. However, it is compiled only if USB is set, but it is required for other drivers (FSL_ESDHC), too. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Andy Fleming <afleming@gmail.com> CC: Dirk Behme <dirk.behme@de.bosch.com> CC: Marek Vasut <marex@denx.de> CC: Wolfgang Denk <wd@denx.de> Added MPC83xx version. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2012-07-08-152/+336
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E powerpc/mpc85xx: Workaround for erratum CPU_A011 powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER() powerpc/P4080: Check SVR for CPU22 workaround lib/powerpc: addrmap_phys_to_virt() should return a pointer powerpc/85xx: clean up P1022DS board configuration header file powerpc/85xx: fdt_set_phy_handle() should return an error code powerpc/85xx: minor clean-ups to the P2020DS board header file powerpc/p1010rdb: add readme document for p1010rdb powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting powerpc/mpc85xx:Add debugger support for e500v2 SoC powerpc/85xx:Fix NAND code base to support debugger powerpc/85xx:Make debug exception vector accessible powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger PATCH 1/4][v4] doc:Add documentation for e500 external debugger support powerpc/p1010rdb: update mux config of p1010rdb board powerpc/mpc85xx:Add BSC9131 RDB Support powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support powerpc/85xx: Add USB device-tree fixup for various platforms Signed-off-by: Wolfgang Denk <wd@denx.de>
| * powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040EYork Sun2012-07-06-7/+4
| | | | | | | | | | | | Fix SVR checking for commit acf3f8da. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Workaround for erratum CPU_A011York Sun2012-07-06-10/+39
| | | | | | | | | | | | | | | | | | Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0. It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the same workaround as erratum CPU22. Rearrange registers usage in assembly code to avoid accidental overwriting. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()York Sun2012-07-06-99/+13
| | | | | | | | | | | | | | | | We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER(). This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with encryption. Remove all _E entries from SVR list and CPU list. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/P4080: Check SVR for CPU22 workaroundYork Sun2012-07-06-4/+15
| | | | | | | | | | | | Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only. Signed-off-by: York Sun <yorksun@freescale.com>
| * lib/powerpc: addrmap_phys_to_virt() should return a pointerTimur Tabi2012-07-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | addrmap_phys_to_virt() converts a physical address (phys_addr_t) to a virtual address, so it should return a pointer instead of an unsigned long. Its counterpart, addrmap_virt_to_phys(), takes a pointer, so now they're orthogonal. The only caller of addrmap_phys_to_virt() converts the return value to a pointer anyway. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address settingPrabhakar Kushwaha2012-07-06-26/+0
| | | | | | | | | | | | | | | | | | | | During NAND_SPL boot, base address and different register are programmed default by corresponding NAND controllers(eLBC/IFC). These settings are sufficient enough for NAND SPL. Avoid updating these register.They will be programmed during NAND RAMBOOT. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * powerpc/mpc85xx:Add debugger support for e500v2 SoCPrabhakar Kushwaha2012-07-06-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some restrictions on external debugging (JTAG). So define CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be used during boot to work around the limitations. Please refer doc/README.mpc85xx for more information Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * powerpc/85xx:Fix NAND code base to support debuggerPrabhakar Kushwaha2012-07-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR + IVOR15 should be valid fetchable OP code address. As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to any fetchable valid data Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * powerpc/85xx:Make debug exception vector accessiblePrabhakar Kushwaha2012-07-06-6/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR + IVOR15) to have valid and fetchable OP code. 1) While executing in translated space (AS=1), whenever a debug exception is generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to fetch an instruction from the debug exception vector (IVPR + IVOR15); since now we are in AS=0, the application needs to ensure the proper TLB configuration to have (IVOR + IVOR15) accessible from AS=0 also. Create a temporary TLB in AS0 to make sure debug exception verctor is accessible on debug exception. 2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * powerpc/85xx:Fix MSR[DE] bit in MSR to support debuggerPrabhakar Kushwaha2012-07-06-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Debugging of e500 and e500v1 processer requires MSR[DE] bit to be set always. Where MSR = Machine State register Make sure of MSR[DE] bit is set uniformaly across the different execution address space i.e. AS0 and AS1. Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Catalin Udma <catalin.udma@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor SupportPrabhakar Kushwaha2012-07-06-3/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - BSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. - BSC9130 is exactly same as BSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131). - BSC9231 is similar to BSC9131 except no MAPLE The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. This patch takes care of code pertaining to power side functionality only. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc/mpc83xx: fix copyright string in serdes.cTimur Tabi2012-07-03-1/+1
|/ | | | | | | | The misspelling of "semiconductor" causes some internal copyright analysis tools to complain. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* MPC8xxx: Define cache ops for USBMarek Vasut2012-06-07-0/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch conditionally defines flush_dcache_range() and invalidate_dcache_range() on MPC8xxx, to avoid EHCI complaining, resulting in the following output: $ ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- ./MAKEALL MPC8572DS Configuring for MPC8572DS board... make: *** [u-boot] Error 1 powerpc-linux-gnu-size: './u-boot': No such file e1000.c: In function ‘e1000_initialize’: e1000.c:5264:13: warning: assignment from incompatible pointer type [enabled by default] tsec.c: In function ‘tsec_initialize’: tsec.c:638:12: warning: assignment from incompatible pointer type [enabled by default] drivers/usb/host/libusb_host.o: In function `ehci_td_buffer': /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:186: undefined reference to `flush_dcache_range' drivers/usb/host/libusb_host.o: In function `ehci_submit_async': /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:346: undefined reference to `flush_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:348: undefined reference to `flush_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:349: undefined reference to `flush_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:372: undefined reference to `invalidate_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:374: undefined reference to `invalidate_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:376: undefined reference to `invalidate_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:386: undefined reference to `invalidate_dcache_range' make: *** [u-boot] Error 1 --------------------- SUMMARY ---------------------------- Boards compiled: 1 Boards with errors: 1 ( MPC8572DS ) ---------------------------------------------------------- Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Anatolij Gustschin <agust@denx.de>
* net: cosmetic: Un-typedef Ethernet_tJoe Hershberger2012-05-23-9/+8
| | | | | | | Separate the Ethernet header from the 802 header. Base the size constants on the structs. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* net: Encapsulate CDP packet identificationJoe Hershberger2012-05-23-1/+1
| | | | | | Checking for CDP packets should be encapsulated, not copied code. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* arch/powerpc/cpu/mpc8260/ether_scc.c: Fix compile warningJoe Hershberger2012-05-22-1/+1
| | | | | | | | Fix this: ether_scc.c: In function 'mpc82xx_scc_enet_initialize': ether_scc.c:377:14: warning: assignment from incompatible pointer type Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* arch/powerpc/cpu/mpc85xx/ether_fcc.c: Fix compile warningJoe Hershberger2012-05-22-1/+1
| | | | | | | | Fix this: ether_fcc.c: In function 'fec_initialize': ether_fcc.c:453:15: warning: assignment from incompatible pointer type Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* arch/powerpc/cpu/mpc8260/ether_fcc.c: Fix compile warningJoe Hershberger2012-05-22-1/+1
| | | | | | | | Fix this: ether_fcc.c: In function 'fec_initialize': ether_fcc.c:390:15: warning: assignment from incompatible pointer type Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* arch/powerpc/cpu/mpc8220/fec.c: Fix compile warningJoe Hershberger2012-05-22-3/+2
| | | | | | | | | | | Fix this: fec.c: In function 'mpc8220_fec_recv': fec.c:791:9: warning: passing argument 1 of 'NetReceive' discards qualifiers from pointer target type include/net.h:438:13: note: expected 'uchar *' but argument is of type 'volatile uchar *' fec.c: In function 'mpc8220_fec_initialize': fec.c:839:12: warning: assignment from incompatible pointer type Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* MPC8xx: fix "Remove volatile from net API" aftermathWolfgang Denk2012-05-22-5/+5
| | | | | | | | | | | | | | | | | Commit db288a9 "net: Remove volatile from net API" caused a number of build warnings: fec.c: In function 'fec_initialize': fec.c:183:13: warning: assignment from incompatible pointer type [enabled by default] fec.c: In function 'fec_recv': fec.c:284:5: warning: passing argument 1 of 'NetReceive' discards 'volatile' qualifier from pointer target type [enabled by default] /home/wd/git/u-boot/work/include/net.h:433:13: note: expected 'uchar *' but argument is of type 'volatile uchar *' scc.c: In function 'scc_initialize': scc.c:85:14: warning: assignment from incompatible pointer type [enabled by default] Fix these. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
* Merge branch 'master' of git://git.denx.de/u-boot-nand-flashWolfgang Denk2012-05-20-3/+6
|\ | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-nand-flash: NAND: Remove ONFI detection message to from bootup log driver/mtd:IFC: Fix possible memory leak driver/mtd: IFC NAND: Add support of ONFI NAND flash mtd, nand: move some printfs to debug output. nand_util: correct YAFFS image write function powerpc/85xx: fix NAND boot linker scripts for -fpic nand: extend .raw accesses to work on multiple pages
| * powerpc/85xx: fix NAND boot linker scripts for -fpicScott Wood2012-05-18-3/+6
| | | | | | | | | | | | | | | | GOT is now handled the way the main u-boot.lds does it. Without this, the boot hangs when built with newer GCC (since 4.6). Older toolchains hid the issue by converting -fpic to -fPIC. Signed-off-by: Scott Wood <scottwood@freescale.com>
* | net: move bootfile init into eth_initializeMike Frysinger2012-05-15-8/+0
| | | | | | | | | | | | | | | | All arches init this the same way, so move the logic into the core net code to avoid duplicating it everywhere else. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: punt bd->bi_ip_addrMike Frysinger2012-05-15-4/+0
|/ | | | | | | | | This field gets read in one place (by "bdinfo"), and we can replace that with getenv("ipaddr"). After all, the bi_ip_addr field is kept up-to-date implicitly with the value of the ipaddr env var. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSRTimur Tabi2012-04-24-2/+6
| | | | | | | The CCSR relocation code in start.S writes to MAS7 on all e500 parts, but that register does not exist on e500v1. Signed-off-by: Timur Tabi <timur@freescale.com>
* powerpc/corenet_ds: Slave core in holdoff when boot from SRIOLiu Gang2012-04-24-0/+131
| | | | | | | | | | | | | | | | | | When boot from SRIO, slave's core can be in holdoff after powered on for some specific requirements. Master can release the slave's core at the right time by SRIO interface. Master needs to: 1. Set outbound SRIO windows in order to configure slave's registers for the core's releasing. 2. Check the SRIO port status when release slave core, if no errors, will implement the process of the slave core's releasing. Slave needs to: 1. Set all the cores in holdoff by RCW. 2. Be powered on before master's boot. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc/corenet_ds: Slave reads ENV from master when boot from SRIOLiu Gang2012-04-24-0/+17
| | | | | | | | | | | | | | | | | | | | When boot from SRIO, slave's ENV can be stored in master's memory space, then slave can fetch the ENV through SRIO interface. NOTE: Because the slave can not erase, write master's NOR flash by SRIO interface, so it can not modify the ENV parameters stored in master's NOR flash using "saveenv" or other commands. Master needs to: 1. Put the slave's ENV into it's own memory space. 2. Set an inbound SRIO window covered slave's ENV stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode and ENV from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc/corenet_ds: Slave uploads ucode when boot from SRIOLiu Gang2012-04-24-4/+21
| | | | | | | | | | | | | | | | | When boot from SRIO, slave's ucode can be stored in master's memory space, then slave can fetch the ucode image through SRIO interface. For the corenet platform, ucode is for Fman. Master needs to: 1. Put the slave's ucode image into it's own memory space. 2. Set an inbound SRIO window covered slave's ucode stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc/corenet_ds: Master module for boot from SRIOLiu Gang2012-04-24-2/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc/srio: Rewrite the struct ccsr_rioLiu Gang2012-04-24-160/+270
| | | | | | | Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
* powerpc/85xx:Fix lds for nand boot debug infoPrabhakar Kushwaha2012-04-24-2/+2
| | | | | | | | | | | | | | | | | | Currently "u-boot", the elf file generated via u-boot-nand.lds does not contain required debug information i.e. .debug_{line, info, abbrev, aranges, ranges} into their respective _global_ sections. The original ld script line arch/powerpc/cpu/mpc85xx/start.o KEEP(*(.bootpg)) is not entirely correct because the start.o file is already processed by the linker,therefore the file wildcard in "KEEP(*(.bootpg))" will not process start.o again for bootpg. So Fix u-boot-nand.lds to generate these debug information. Signed-off-by: Anmol Paralkar <b07584@freescale.com> Signed-off-by: John Russo <John.Russo@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx:Avoid vector table compilation for nand_splPrabhakar Kushwaha2012-04-24-0/+6
| | | | | | | | NAND SPL code never compile the vector table. So no need to setup interrupt vector table for NAND SPL. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx:Fix IVORs addr after vector table relocationPrabhakar Kushwaha2012-04-24-0/+33
| | | | | | | | | | | After relocation of vector table in SDRAM's lower address, IVORs value should be updated with new handler addresses. As vector tables are relocated to 0x100,0x200... 0xf00 address in DDR.IVORs are updated with 0x100, 0x200,....f00 hard-coded values. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx:Avoid hardcoded vector address for IVORsPrabhakar Kushwaha2012-04-24-31/+34
| | | | | | | | | | | | For e500 and e500v2 architecturees processor IVPR address should be alinged on 64K boundary. in start.S, CONFIG_SYS_MONITOR_BASE is stored blindly in IVPR assuming it to be 64K aligned. It may not be true always. If it is not aligned, IVPR + IVORs may not point to an exception handler. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* usb: replace wait_ms() with mdelay()Mike Frysinger2012-03-19-6/+6
| | | | | | | | | | | | | | | | | | | | | | | Common code has a mdelay() func, so use that instead of the usb-specific wait_ms() func. This also fixes the build errors: ohci-hcd.c: In function 'submit_common_msg': /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1519:9: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1816:10: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1827:10: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1844:10: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1563:11: sorry, unimplemented: called from here /usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available ohci-hcd.c:1583:9: sorry, unimplemented: called from here make[1]: *** [ohci-hcd.o] Error 1 Signed-off-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Marek Vasut <marex@denx.de>
* bootstage: Replace show_boot_progress/error() with bootstage_...()Simon Glass2012-03-18-2/+2
| | | | | | | These calls should not be made directly any more, since bootstage will call the show_boot_...() functions as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* bootstage: Convert progress numbers 20-41 to enumsSimon Glass2012-03-18-1/+1
| | | | Signed-off-by: Simon Glass <sjg@chromium.org>
* bootstage: Use show_boot_error() for -ve progress numbersSimon Glass2012-03-18-1/+1
| | | | | | | | Rather than the caller negating our progress numbers to indicate an error has occurred, which seems hacky, add a function to indicate this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* bootstage: Make use of BOOTSTAGE_ID_RUN_OS in show_boot_progress()Simon Glass2012-03-18-1/+1
| | | | | | | | | This changes the number 15 as used in boot_stage_progress() to use the new name provided for it. This is a separate patch because it touches so many files. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* ppc: Change memsz variable to signed charSimon Glass2012-03-03-4/+3
| | | | | | | | This seems to be unsigned char for no good reason. Tidy this up and remove the casts. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* powerpc/8xxx:Add MPH controller support in USB device-tree fixupramneek mehresh2012-02-15-10/+19
| | | | | | | | Add support for fixing usb mode and phy type for MPH(Multi Port Host) USB controllers in device-tree nodes. Required for socs like P3060, P5020, etc having MPH USB controller Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* powerpc/8xxx: Cleanup USB device-tree fixupramneek mehresh2012-02-15-6/+12
| | | | | | | | | Some code cleanup done for USB device-tree fixup: - handling error value returned from fdt_fixup_usb_mode_phy_type() - using ARRAY_SIZE macro - using snprintf instead of sprintf Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2012-01-13-0/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: fsl_lbc: add printout of LCRR and LBCR to local bus regs sbc8548: Fix up local bus init to be frequency aware sbc8548: enable support for hardware SPD errata workaround sbc8548: relocate fixed ddr init code to ddr.c file sbc8548: Make enabling SPD RAM configuration work sbc8548: Fix LBC SDRAM initialization settings sbc8548: enable ability to boot from alternate flash sbc8548: relocate 64MB user flash to sane boundary Revert "SBC8548: fix address mask to allow 64M flash" MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM eXMeritus HWW-1U-1A: Minor environment variable tweaks
| * fsl_lbc: add printout of LCRR and LBCR to local bus regsPaul Gortmaker2012-01-13-0/+4
| | | | | | | | | | | | | | | | It can be handy to have these in the output when trying to debug odd behaviour. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | mpc83xx: Add a GPIO driver for the MPC83XX familyJoe Hershberger2012-01-09-0/+40
|/ | | | | | Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* powerpc/mpc83xx: set TXEQA/TXEQE value for mpc837XE sataJerry Huang2011-12-12-1/+10
| | | | | | | | | | | | In the current u-boot code, the value of these fields are the reserved value (0b100), through the signal integrity measurement on freescale's board with these reserved setting, the signal eye is out of the recommended spec for non-transition amplitude at 500mV nominal. According to the errata for MPC8379E, we should make a change to the recommended setting from essentially nothing at this time to 0b001 for SATA. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
generated by cgit v1.1 at 2024-12-26 05:50:05 +0000