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* powerpc: Change bi_baudrate and global data baudrate to intSimon Glass2012-10-19-2/+2
| | | | | | | These don't need to be longs, so change them. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* split mpc8xx hooks from cmd_ide.cPavel Herrmann2012-10-17-0/+233
| | | | | | | | | | | | | move most of mpc8xx hooks from cmd_ide.c into ide_preinit() and newly created ide_init_postreset() (invoked after calling ide_reset after ide_preinit), some cleanup to make checkpatch happy, enable IDE init hooks in configs of affected boards. confusingly, these hooks are used by more than just mpc8xx-based boards, and therefore are placed in arch/ppc/lib/ note: checkpatch still emits warnings about using volatile Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
* serial: Use default_serial_puts() in driversMarek Vasut2012-10-17-41/+5
| | | | | | | | | | Replace the in-place ad-hoc implementation of serial_puts() within the drivers with default_serial_puts() call. This cuts down on the code duplication quite a bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com>
* mpc82xx: Remove BMW board portStefan Roese2012-10-17-9/+4
| | | | | | | | | | | As the board seems to be unmaintained for some time, lets remove the support in mainline completely. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: James F. Dougherty <jfd@broadcom.com> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Marek Vasut <marex@denx.de>
* usb: lowlevel interface change to support multiple controllersLucas Stach2012-10-15-4/+4
| | | | | | | | | | | Carry an index in the lowlevel usb functions to make specify the respective usb controller. Also pass through an controller struct from lowlevel_init to the creation of the root usb device of this controller. Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Marek Vasut <marex@denx.de>
* ppc4xx: Remove AP1000 board supportStefan Roese2012-10-15-15/+0
| | | | | | | | | As the board seems to be unmaintained for some time, lets remove the support in mainline completely. Signed-off-by: Stefan Roese <sr@denx.de> Cc: James MacAulay <james.macaulay@amirix.com> Acked-by: Marek Vasut <marex@denx.de>
* ppc4xx: Remove ML2 board supportStefan Roese2012-10-15-1/+1
| | | | | | | | | As the board seems to be unmaintained for some time, lets remove the support in mainline completely. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter De Schrijver <p2@mind.be> Acked-by: Marek Vasut <marex@denx.de>
* ppc4xx: Remove IOP480 supportStefan Roese2012-10-15-400/+2
| | | | | | | | | | Since the IOP480 (PPC401/3 variant from PLX) is only used on 2 boards that are not actively maintained, lets remove support for it completely. This way the ppc4xx code will get a bit cleaner. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu> Acked-by: Marek Vasut <marex@denx.de>
* serial: Remove CONFIG_SERIAL_MULTI from remaining sourcesMarek Vasut2012-10-15-2/+0
| | | | | | | | | | | | Remove the parts depending either on disabled CONFIG_SERIAL_MULTI or ifdefs around CONFIG_SERIAL_MULTI parts since CONFIG_SERIAL_MULTI is now enabled by default. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de>
* serial: Remove CONFIG_SERIAL_MULTI from serial driversMarek Vasut2012-10-15-369/+39
| | | | | | | | | | | | Remove the support for not-CONFIG_SERIAL_MULTI part from serial port drivers and some board files. Since CONFIG_SERIAL_MULTI is now enabled by default, that part is a dead code. Remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
* serial: powerpc: Implement CONFIG_SERIAL_MULTI into iop480 serial driverMarek Vasut2012-10-15-6/+59
| | | | | | | | | | | | | | Implement support for CONFIG_SERIAL_MULTI into iop480 serial driver. This driver was so far only usable directly, but this patch also adds support for the multi method. This allows using more than one serial driver alongside the iop480 driver. Also, add a weak implementation of default_serial_console() returning this driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de>
* serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc85xx serial driverMarek Vasut2012-10-15-11/+60
| | | | | | | | | | | | | | Implement support for CONFIG_SERIAL_MULTI into mpc85xx serial driver. This driver was so far only usable directly, but this patch also adds support for the multi method. This allows using more than one serial driver alongside the mpc85xx driver. Also, add a weak implementation of default_serial_console() returning this driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de>
* serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc8260 serial driversMarek Vasut2012-10-15-22/+120
| | | | | | | | | | | | | | Implement support for CONFIG_SERIAL_MULTI into both SCC and SMC mpc8260 serial drivers. These drivers were so far only usable directly, but this patch also adds support for the multi method. This allows using more than one serial driver alongside the mpc8260 drivers. Also, add a weak implementation of default_serial_console() returning this driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de>
* serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc8220 serial driverMarek Vasut2012-10-15-6/+61
| | | | | | | | | | | | | | Implement support for CONFIG_SERIAL_MULTI into mpc8220 serial driver. This driver was so far only usable directly, but this patch also adds support for the multi method. This allows using more than one serial driver alongside the mpc8220 driver. Also, add a weak implementation of default_serial_console() returning this driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de>
* serial: powerpc: Implement CONFIG_SERIAL_MULTI into mpc5xx serial driverMarek Vasut2012-10-15-21/+74
| | | | | | | | | | | | | | Implement support for CONFIG_SERIAL_MULTI into mpc5xx serial driver. This driver was so far only usable directly, but this patch also adds support for the multi method. This allows using more than one serial driver alongside the mpc5xx driver. Also, add a weak implementation of default_serial_console() returning this driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de>
* serial: mpc512x: Move serial registration from serial_initialize()Marek Vasut2012-10-15-0/+16
| | | | | | | | | | | | | | | | | | | | | | | Move the registration of serialN_device ports from default serial_initialize() into driver specific function called from serial_initialize(). This slims down the serial_initialize() call to a bare tracker of all possible serial port registration routines in U-Boot. The newly implemented mpc512x_serial_initialize() function, which is implemented inside of the mpc512x serial driver allows encapsulation of serialN_device within the mpc512x serial driver itself. Also, remove the exports of serialN_device from include/serial.h as they are no longer needed. This is simply because the implementation of default_serial_console() is wrapped into the mpx512x serial driver and the default console is picked by CONFIG_SERIAL<N> macro in config file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de>
* serial: mpc8xx: Move serial registration from serial_initialize()Marek Vasut2012-10-15-0/+11
| | | | | | | | | | | | | | | | | | | Move the registration of serial_smc and serial_scc ports from default serial_initialize() into CPU specific function called from serial_initialize(). This slims down the serial_initialize() call to a bare tracker of all possible serial port registration routines in U-Boot. The exports of both serial_scc_device and serial_smc_device can not yet be removed as they are still used in default_serial_console() calls. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Mike Frysinger <vapier@gentoo.org>
* serial: Properly spell out the structure member names of serial_driverMarek Vasut2012-10-15-41/+41
| | | | | | | | | | | | | | | | | Properly spell out the whole structure member names when an initialized varible is instantiated from the struct serial_driver. In case the structure definition for struct serial_driver undergoes reordering, there will be no impact on variables defined based on this structure. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tom Rini <trini@ti.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Mike Frysinger <vapier@gentoo.org> Cc: C Nauman <cnauman@diagraph.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Michal Simek <monstr@monstr.eu>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2012-09-25-926/+1359
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| * Revert "powerpc: Fix declaration type for I/O functions"Andy Fleming2012-08-23-10/+10
| | | | | | | | This reverts commit 20959471b5d07fdeb8603b918d80385aa2954711.
| * powerpc/85xx: clear out TLB on bootScott Wood2012-08-23-33/+48
| | | | | | | | | | | | | | | | Instead of just shooting down the entry that covers CCSR, clear out every TLB entry that isn't the one that we're executing out of. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Move HWCONFIG_BUFFER_SIZE into config.hYork Sun2012-08-23-5/+4
| | | | | | | | | | | | | | | | | | | | Before proper environment is setup, we extract hwconfig and put it into a buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to accommodate longer string. Since this macro is used in multiple files, we move it into arch/powerpc/include/asm/config.h. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx DDR: Fix interactive DDR debuggingYork Sun2012-08-23-2/+2
| | | | | | | | | | | | | | | | Add one more argument to call function readline_into_buffer(). Fix print SPD format for negative values. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx DDR: Fall back to raw timing for first controller onlyYork Sun2012-08-23-1/+1
| | | | | | | | | | | | | | | | Only the first DIMM of first controller should fall back to raw timing parameters if SPD is missing or corrupted. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx DDR: Fix CAS latency calculationYork Sun2012-08-23-2/+4
| | | | | | | | | | | | | | Empty slot should be skipped when calculating CAS latency. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Fix bug for extended DDR timingYork Sun2012-08-23-20/+43
| | | | | | | | | | | | | | | | Faster DDR3 timing requires parameters exceeding previously defined range. Extended parameters are fixed. Added some debug messages. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleavingYork Sun2012-08-23-318/+455
| | | | | | | | | | | | | | | | Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Add support for cas latency 12 and aboveYork Sun2012-08-23-7/+21
| | | | | | | | | | | | | | | | Required by JEDEC 79-3E for high speed DDR3. Also change "CSn disabled" message to debug. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Add fine timing support for DDR3York Sun2012-08-23-12/+36
| | | | | | | | | | | | | | | | When the DDR3 speed goes higher, we need to utilize fine offset from SPD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Skip zero values for DDR debug registersYork Sun2012-08-23-3/+11
| | | | | | | | | | | | | | | | | | | | | | Some debug registers have non-zero default out of reset. If software is not setting debug registers, skip writing to them to avoid unnecessary overriding. Also add debug messages for workarounds and debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: fix core id for multicore bootingYork Sun2012-08-23-6/+53
| | | | | | | | | | | | | | | | | | | | For the cores with multiple threads, we need to figure out which physical core a thread belongs. To match the core ids, update PIR registers and spin tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Added new ext fields to IFCKumar Gala2012-08-23-6/+24
| | | | | | | | | | | | | | | | | | | | In case more than 32 bit address is used, the EXT bit should be set. Need to fix up address map for IFC #CS for 4, also need to move # of IFC banks into config_mpc85xx.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Add IFC offset for DPAA/Corenet platformsKumar Gala2012-08-23-0/+1
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Add e6500 processor detectionKumar Gala2012-08-23-0/+4
| | | | | | | | | | Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: use topology registers to calculate number of coresYork Sun2012-08-23-9/+70
| | | | | | | | | | | | | | | | | | We have actual topology infomation to find out exactly which core is present. Calculate the number of cores if not specified. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Add immap for topology and rcpm registersYork Sun2012-08-23-1/+87
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Add IFC LAW target ID for FSL High-End SoCPrabhakar Kushwaha2012-08-23-0/+1
| | | | | | | | | | | | | | | | | | | | Freescale's High-End SoC are going to have Integrated Flash controller (IFC)'s support. So add IFC LAW target ID support for High-End SoC or corenet SoC. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx:Enable debugger support to missed e500v2 SoCPrabhakar Kushwaha2012-08-23-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some restrictions on external debugging (JTAG). Need to define define CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be used during boot to work around the limitations. Enable missed e500v2 SoC i.e. MPC8536, MPC8544, MPC8548 and MPC8572 for debug support. Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/fsl-corenet: work around erratum A004510Scott Wood2012-08-23-0/+330
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A004510 says that under certain load conditions, modified cache lines can be discarded, causing data corruption. To work around this, several CCSR and DCSR register updates need to be made in a careful manner, so that there is no other transaction in corenet when the update is made. The update is made from a locked cacheline, with a delay before to flush any previous activity, and a delay after to flush the CCSR/DCSR update. We can't use a readback because that would be another corenet transaction, which is not allowed. We lock the subsequent cacheline to prevent it from being fetched while we're executing the previous cacheline. It is filled with nops so that a branch doesn't cause us to fetch another cacheline. Ordinarily we are running in a cache-inhibited mapping at this point, so we temporarily change that. We make it guarded so that we should never see a speculative load, and we never do an explicit load. Thus, only the I-cache should ever fill from this mapping, and we flush/unlock it afterward. Thus we should avoid problems from any potential cache aliasing between inhibited and non-inhibited mappings. NOTE that if PAMU is used with this patch, it will need to use a dedicated LAW as described in the erratum. This is the responsibility of the OS that sets up PAMU. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/fsl-corenet: remove dead variant symbolsScott Wood2012-08-23-69/+4
| | | | | | | | | | | | | | | | | | | | | | These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: remove support for the Freescale P3060Timur Tabi2012-08-23-261/+2
| | | | | | | | | | | | | | | | The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: add support for FM2 DTSEC5Timur Tabi2012-08-23-0/+8
| | | | | | | | | | | | | | | | Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * p1014rdb: set ddr bus width properly depending on SVRMatthew McClintock2012-08-23-0/+1
| | | | | | | | | | | | | | | | | | | | Currently, for NAND boot for the P1010/4RDB we hard code the DDR configuration. We can still dynamically set the DDR bus width in the nand spl so the P1010/4RDB boards can boot from the same u-boot image Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Remove P1015 and P1016 from CPU listYork Sun2012-08-23-39/+2
| | | | | | | | | | | | | | | | P1015 is the same as P1011 and P1016 is the same as P1012 from software point of view. They have different packages but share SVRs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/corenet_ds: Master module for boot from PCIELiu Gang2012-08-23-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2" or "PCIE3" using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macroLiu Gang2012-08-23-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build targetLiu Gang2012-08-23-99/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of the SRIOBOOT_MASTER build target, and to support for serving as a SRIO boot master via environment variable. Set the environment variable "bootmaster" to "SRIO1" or "SRIO2" using the following command: setenv bootmaster SRIO1 saveenv The "bootmaster" will enable the function of the SRIO boot master, and this has the following advantages compared with SRIOBOOT_MASTER build configuration: 1. Reduce a build configuration item in boards.cfg file. No longer need to build a special image for master, just use a normal target image and set the "bootmaster" variable. 2. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just set the corresponding value to "bootmaster" based on the using SRIO port. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditionalYork Sun2012-08-23-3/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This erratum applies to the following SoCs: P4080 rev 1.0, 2.0, fixed in rev 3.0 P2041 rev 1.0, 1.1, fixed in rev 2.0 P3041 rev 1.0, 1.1, fixed in rev 2.0. Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround may degrade performance. P4080 erratum CPU22 shares the same workaround. So it is always enabled for P4080. For other SoCs, it can be disabled by hwconfig with syntax: fsl_cpu_a011:disable Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc: Stack Pointer not properly alignedJoakim Tjernlund2012-08-22-3/+2
| | | | | | | | | | | | | | | | | | The code first aligns the SP to 16 then subtract 8, making it 8 bytes aligned. Furthermore the initial stack frame not quite correct either. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * mpc85xx: Initial SP alignment is wrong.Joakim Tjernlund2012-08-22-11/+5
| | | | | | | | | | | | | | | | | | | | | | | | PowerPC mandates SP to be 16 bytes aligned. Furthermore, a stack frame is added, pointing to the reset vector which may in the way when gdb is walking the stack because the reset vector may not accessible depending on emulator settings. Also use a temp register so gdb doesn't pick up intermediate values. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit v1.1 at 2024-11-05 12:46:28 +0000