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* powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)Kumar Gala2011-01-14-1/+10
| | | | | | | CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr codeKumar Gala2011-01-14-2/+23
| | | | | | | | Move the parsing of hwconfig to determine if to use spd into common code so we can share it across all boards instead of duplicating it everywhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)Roy Zang2011-01-14-0/+11
| | | | | | | | | | False multi-bit ECC errors will be reported by the eSDHC buffer which can trigger a reset request. We disable all ECC error checking on SDHC. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)Roy Zang2011-01-14-0/+3
| | | | | | | | | | | The default value of the SRS, VS18 and VS30 and ADMAS fields in the host controller capabilities register (HOSTCAPBLT) are incorrect. The default of these bits should be zero instead of one. Clear these bits out when we read HOSTCAPBLT. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080)Jerry Huang2011-01-14-1/+4
| | | | | | | | | Do not issue a manual asynchronous CMD12. Instead, use a (software) synchronous CMD12 or AUTOCMD12 to abort data transfer. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/86xx: Enable common SRIO init codeKumar Gala2011-01-14-3/+15
| | | | | | | | Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Refactor SRIO initialization into common codeKumar Gala2011-01-14-3/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* fsl_pci: Update PCIe boot ouputPeter Tyser2011-01-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change does the following: - Adds printing of negotiated link width. This information can be useful when debugging PCIe issues. - Makes it optional for boards to implement board_serdes_name(). Previously boards that did not implement it would print unsightly output such as "PCIE1: Connected to <NULL>..." - Rewords the PCIe boot output to reduce line length and to make it clear that the "base address XYZ" value refers to the base address of the internal processor PCIe registers and not a standard PCI BAR value. - Changes "PCIE" output to the standard "PCIe" Before change: PCIE1: connected to <NULL> as Root Complex (base addr ef008000) 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 05 PCIE2: connected to <NULL> as Endpoint (base addr ef009000) PCIE2: Bus 06 - 06 After change: PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device PCIe1: Bus 00 - 05 PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 PCIe2: Bus 06 - 06 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/fsl-pci: Add generic code to setup PCIe controllersKumar Gala2011-01-14-0/+10
| | | | | | | | | | | | | | | | | | Since all the PCIe controllers are connected over SERDES on the SoCs we can utilize is_serdes_configured() to determine if a controller is enabled. After which we can setup the ATMUs and LAWs for the controller in a common fashion and allow board code to specify what the controller is connected to for reporting reasons. We also provide a per controller (rather than all) for some systems that may have special requirements. Finally, we refactor the code used by the P1022DS to utilize the new generic code. Based on patch by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/fsl-pci: Determine pci_controller based on cfg addr for dts fixupKumar Gala2011-01-14-40/+3
| | | | | | | | | | | | | | Previously we passed in a specifically named struct pci_controller to determine if we had setup the particular PCI bus. Now we can search for the struct so we dont have to depend on the name or the struct being statically allocated. Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct back by searching for it means we can do things like dynamically allocate them or not have to expose the static structures to all users. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* powerpc/85xx: Fix bug in dcache_disableKumar Gala2011-01-14-2/+2
| | | | | | | | We set the L1 dache register with a bogus register value. Need to be using 'r3' instead of 'r0'. Reported-by: John Traill <john.traill@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC8xxx DDR: align informational printsBecky Bruce2011-01-14-2/+3
| | | | | | | | | | | | | | | | | | | | Add spaces to cause the informational prints to line up with the ones from init_func_ram() in board.c. Output now looks like this: .... DRAM: Detected 4096 MB of memory This U-Boot only supports < 4G of DDR You could rebuild it with CONFIG_PHYS_64BIT DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC off) .... The prints from lbc_sdram_init() have also been modified to line line up and changed to start with "LBC SDRAM" instead of the confusing "SDRAM". Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx boards: Rename CONFIG_DDR_DLL to CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_INBecky Bruce2011-01-14-1/+4
| | | | | | | | | This config option is for an erratum workaround; rename it to be more clear. Also, drop it from config files don't need it and were undefining it. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: rename sdram_init() lbc_sdram_init()Becky Bruce2011-01-14-4/+4
| | | | | | | | sdram_init() is used to initialize sdram on the lbc. Rename it accordingly. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx boards: initdram() cleanup/bugfixBecky Bruce2011-01-14-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences: 1) DDR tlbs for the fixed_sdram case were set up in initdram() on some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner. 2) Parts that require the DDR11 erratum workaround had different implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad. The xpedite boards had a common/fsl_8xxx_ddr.c; with this change only the 517 board uses this so I have moved the ddr code into that board's directory in xpedite517x.c Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx/tlb.c: Allow platforms to specify wimge bitsBecky Bruce2011-01-14-1/+5
| | | | | | | | | | | | | Some platforms might want to override the default wimge=0 for DDR. Add CONFIG_SYS_PPC_DDR_WIMGE for those platforms to use. This will initially only be used by TQM85xx, but could be useful for other boards or testing going forward. Note that the name of this define is not 85xx-specific. WIMGE is a fairly universal concept, so any ppc platforms that require different WIMGE settings for DDR can use the same #define. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Replace is_fsl_pci_cfg with is_serdes_configuredKumar Gala2011-01-14-207/+0
| | | | | | | Now that we have serdes support for all 85xx/86xx/Pxxx chips we can replace the is_fsl_pci_cfg() code with the is_serdes_configured(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix wrong SVR value for MPC8567 and MPC8567E processorsPiergiorgio Beruto2011-01-14-2/+2
| | | | | Signed-off-by: Piergiorgio Beruto <piergiorgio.beruto@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add is_serdes_configured() support for P1021 SERDESKumar Gala2011-01-14-0/+68
| | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add is_serdes_configured() support for MPC8544 SERDESKumar Gala2011-01-14-0/+96
| | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add is_serdes_configured() support for MPC8569 SERDESKumar Gala2011-01-14-0/+75
| | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add is_serdes_configured() support for MPC8568 SERDESKumar Gala2011-01-14-0/+66
| | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add is_serdes_configured() support for MPC8548 SERDESKumar Gala2011-01-14-0/+66
| | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add is_serdes_configured() support for MPC8572 SERDESKumar Gala2011-01-14-0/+82
| | | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Chenhui Zhao <b26998@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add is_serdes_configured() support for P2020 SERDESKumar Gala2011-01-14-0/+75
| | | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/86xx: Add SERDES support on MPC8641 & MPC8610Kumar Gala2011-01-14-1/+186
| | | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. This mimics the code we have in place for the 85xx platforms. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Create a SERDES section in MakefileKumar Gala2011-01-14-2/+5
| | | | | | | Created a section in the Makefile for SoC specific SERDES code. Also added P1013 SERDES (use P1022 SERDES code). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Replace CONFIG_SYS_HAS_SERDES with a weak functionKumar Gala2011-01-14-2/+6
| | | | | | Instead of a #define use a null weak function for fsl_serdes_init Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc4xx: Fix compilation breakage in miiphy.cStefan Roese2011-01-11-1/+1
| | | | | | | | Patch 8ef583a0 [miiphy: convert to linux/mii.h] introduced a small problem in the ppc4xx miiphy.c version. This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
* miiphy: convert to linux/mii.hMike Frysinger2011-01-09-38/+38
| | | | | | | | The include/miiphy.h header duplicates a lot of things from linux/mii.h. So punt all the things that overlap to keep the API simple and to make merging between U-Boot and Linux simpler. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* powerpc: fix register usage in some inline assembly codeTimur Tabi2010-12-17-11/+19
| | | | | | | In some usages of inline assembly, hard-coded registers were specified when a scratch register should have been used instead. Signed-off-by: Timur Tabi <timur@freescale.com>
* 74xx_7xx/mpc86xx/ppmc7xx: Fix do_reset() declarationPeter Tyser2010-12-17-5/+10
| | | | | | | | | | | | | | | | | The following commit: commit 882b7d726febe65579d6502c271412ecb05821d7 Author: Mike Frysinger <vapier@gentoo.org> Date: Wed Oct 20 03:41:17 2010 -0400 do_reset: unify duplicate prototypes missed the 74xx_7xx and mpc86xx arches and the ppmc7xx board do_reset() functions which resulted in build errors such as: cpu.c:128: error: conflicting types for 'do_reset' include/command.h:102: error: previous declaration of 'do_reset' was here Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* PowerPC: Add relocation support for -fpicJoakim Tjernlund2010-12-17-22/+33
| | | | | | | | | By rearranging the linker script we get support for relocation of -fpic for free. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Scott Wood <scottwood@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* xilinx-ppc4xx-generic: Use common u-boot.ldsRicardo Ribalda Delgado2010-12-17-1/+9
| | | | | | | Use common ppc4xx linker script for xilinx ppc440 and ppc405 related boards. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Clarify comment about boot chip-select in start.SStefan Roese2010-12-17-12/+14
| | | | | | | Ths old comment was quite screwed up. Replace it with a new version that should be a bit more descriptive. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of ../master into nextWolfgang Denk2010-12-16-7/+26
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| * mpc83xx: fix pcie enumerationBaidu Boy2010-12-13-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | This patch fix a problem for the pcie enumeration for mpc83xx cpus. Without this we will not get correct value in hose->regions[...]. The pointer *reg in function mpc83xx_pcie_init_bus() shall not be changed. Because we will use this pointer as a parameter to call function mpc83xx_pcie_register_hose(). Signed-off-by: Baidu Boy <liucai.lfn@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * powerpc/85xx: do not reloc l2srbar if CONFIG_FLASH_BASE is not definedHaiying Wang2010-12-01-1/+1
| | | | | | | | | | | | | | | | This fixes the compiling error for the board which doesn't have NOR flash (so CONFIG_FLASH_BASE is not defined) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Introduce CONFIG_SYS_EXTRA_ENV_RELOCKumar Gala2010-11-30-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some systems need to relocate the env_addr pointer early because the location it points to will get invalidated before env_relocate is called. One example is on systems that might use a L2 or L3 cache in SRAM mode and initialize that cache from SRAM mode back to being a cache in cpu_init_r. We set this on the 85xx boards that have support for NAND, SPI, or SDHC/MMC boot support as they use a secondary cache in SRAM mode and need the env_addr pointer relocated since we change from SRAM to normal cache mode in cpu_init_r. Also removed CONFIG_SYS_SPL as its not used anywhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc83xx: Make it boot againJoakim Tjernlund2010-11-30-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | After the removal of COLD/WARM start flags my mpc8321 board didn't boot anymore. Trial and error suggests that map/remap_flash_by_xxx needs to wait after updating LBLAWAR1 to make sure the the change has reached the HW before continuing with the code that depends on it. Final fix suggested by Scott Wood. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | do_reset: unify duplicate prototypesMike Frysinger2010-11-28-3/+1
|/ | | | | | | The duplication of the do_reset prototype has gotten out of hand, and they're not all in sync. Unify them all in command.h. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* ppc4xx: Flush complete dcache in relocate_code()Stefan Roese2010-11-28-6/+7
| | | | | | | | | When the cache is enabled in SDRAM we need to flush not only the global data area but also the bd_info struct in relocate_code. This patch now flushed the complete dcache (all dcache lines) via flush_dcache() instead of adding a flush_dcache_range() call for bd_info since this is faster. Signed-off-by: Stefan Roese <sr@denx.de>
* powerpc: cmd_ecctest: Use return value of cmd_usageThomas Weber2010-11-27-4/+2
| | | | | | | | Use the return value of cmd_usage instead of ignoring this and returning a 1. Signed-off-by: Thomas Weber <weber@corscience.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
* 74xx_7xx: Cleanup for partial linking and --gc-sectionsWolfgang Denk2010-11-27-0/+91
| | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* 8260: Cleanup for partial linking and --gc-sectionsWolfgang Denk2010-11-27-45/+11
| | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* 824x: Cleanup for partial linking and --gc-sectionsWolfgang Denk2010-11-27-43/+10
| | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* 8220: Cleanup for partial linking and --gc-sectionsWolfgang Denk2010-11-27-45/+11
| | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* 5xxx: Cleanup for partial linking and --gc-sectionsWolfgang Denk2010-11-27-102/+43
| | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* 512x: Cleanup for partial linking and --gc-sectionsWolfgang Denk2010-11-27-44/+10
| | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Timur Tabi <timur@freescale.com> Acked-by: Stefan Roese <sr@denx.de>
* 5xx: Cleanup for partial linking and --gc-sectionsWolfgang Denk2010-11-27-53/+16
| | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Stefan Roese <sr@denx.de>
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