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* Timer: Remove reset_timer() for non-Nios2 archesGraeme Russ2011-07-26-5/+0
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* Timer: Remove set_timer completelyGraeme Russ2011-07-26-7/+0
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* powerpc: Fix device tree padding associated with ramdiskKumar Gala2011-07-26-1/+3
| | | | | | | | | | | | | | | | | When booting with a ramdisk we bump the amount of memory reserved for the device tree by FDT_RAMDISK_OVERHEAD. However we did not increase the actual size in the device tree blob to match. Its possible on boundary cases that we dont have enough memory according to the device tree blob and get errors like: WARNING: could not set linux,initrd-end FDT_ERR_NOSPACE We can easily fix this by setting the device tree size at the same time we bump the amount of memory reserved for the device tree. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
* powerpc/mpc85xx: Add clear_ddr_tlbs functionBecky Bruce2011-07-22-11/+33
| | | | | | | | | | | This is useful when we just want to wipe out the TLBs. There's currently a function that resets the ddr tlbs to a different value; it is changed to utilize this function. The new function can be used in conjunction with setup_ddr_tlbs() for a board to temporarily map/unmap the DDR address range as needed. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fman: insert the Fman firmware into the device treeTimur Tabi2011-07-22-0/+123
| | | | | | | | | | | | The Fman device tree node binding allows for the entire Fman firmware binary data to be embedded in the device tree. This eliminates the need to have NOR flash mapped to Linux just so that the Fman driver can see the firmware. The location of the Fman firmware is taken from the 'fman_ucode' environment variable. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: add support the ePAPR "phandle" propertyTimur Tabi2011-07-22-2/+4
| | | | | | | | | | | The ePAPR specification says that phandle properties should be called "phandle", and not "linux,phandle". To facilitate the migration from "linux,phandle" to "phandle", we update fdt_qportal() to use the new function, fdt_create_phandle(). This function abstracts the creation of phandle properties. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix detection of P1017EKumar Gala2011-07-17-1/+1
| | | | | | Had a typo such that P1017E would not be detected correctly. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: remove SERDES4 soft-reset work-aroundTimur Tabi2011-07-11-22/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some P4080 rev1 errata work-arounds, notably erratum SERDES4, required a bank soft-reset after the bank was configured and enabled, even though enabling a bank causes it to reset. Because the reset was required for multiple errata, it was not properly enclosed in an #ifdef, and so was not removed with all the other rev1 errata work-arounds. Erratum SERDES-8 says that the clocks for bank 3 needs to be enabled if bank 2 is enabled, but this was not being done for SERDES protocols 0xF and 0x10. The bank reset also happened to enable bank 3 (apparently an undocumented feature). Simply removing the reset breaks these two protocols. It turns out that every time we call enable_bank(), we do want at least one lane of the bank enabled, either because the bank is supposed to be enabled, or because we need the clock from that bank enabled. For erratum SERDES-A001, we don't want to modify srds_lpd_b[] when we call enable_bank(), because that array is used elsewhere to determine if the bank is available. Note that the side effect of these changes is that the work-arounds for these two errata are now linked. Specifically, if SERDES-A001 is enabled, then we need SERDES-8 enabled as well. Because this was the only SERDES bank soft-reset, there is no need to implement a work-around for erratum SERDES-A003. Also fix an off-by-one error in a printf(). Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Ed Swarthout <swarthou@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Allow override DDR read-to-write turnaround timeYork Sun2011-07-11-0/+6
| | | | | | | Add this option to allow boards to override the default read-to-write turnaround time for better performance. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/8xxx: Update USB mode device tree fixupRamneek Mehresh2011-07-11-12/+65
| | | | | | | | | | | | Modify support for USB mode fixup: - Add common support for USB mode and phy type device tree fix-up for all USB controllers mentioned in hwconfig string - Fetch USB mode and phy type via hwconfig; if not defined in hwconfig, then fetch them from env Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: fix DDR data width checkingYork Sun2011-07-11-8/+27
| | | | | | | | | Checking width before setting DDR controller. SPD for DDR1 and DDR2 has data width and primary sdram width. The latter one has different meaning for DDR3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Adding fallback to raw timing on supported boardsYork Sun2011-07-11-0/+8
| | | | | | | | In case of empty SPD or checksum error, fallback to raw timing on supported boards. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Enable calculation for fixed DDR chipsYork Sun2011-07-11-3/+33
| | | | | | | | | | We used to have fixed parameters for soldered DDR chips. This patch introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing data from DDR chip datasheet, implemneted in board-specific files or header files. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix pin muxing for second USB controllerFelix Radensky2011-07-11-1/+1
| | | | | | | | | | | On P1022/P1013 second USB controller is muxed with second Ethernet controller. The current code to enable second USB fails to properly clear pinmux bits used by ethernet. As a result, Linux freezes when this controller is used. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Add 16-bit support for DDR3York Sun2011-07-11-2/+18
| | | | | | | | Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit DDR devices. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: check SPD length before using part numberYork Sun2011-07-11-1/+2
| | | | | | | | Only use DDR DIMM part number if SPD has valid length, to prevent from display garbage in case SPD doesn't cover these fields. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: adjust DDR burst length and chop accroding to sdram widthYork Sun2011-07-11-4/+20
| | | | | | | | If the bus width is 32-bit, burst chop should be disabled and burst length should be 8. Read from SPD or other source to determine the width. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add P2041 processor supportKumar Gala2011-07-11-0/+26
| | | | | | The P2041 is similar to P2040, however has a 10G port and backside L2 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p2040: Add various p2040 specific informationMingkai Hu2011-07-11-0/+133
| | | | | | | | | | | Add P2040 SoC specific information: * LIODN setup * Portal configuration * etc Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix compile errors if CONFIG_SYS_DPAA_QBMAN isn't setKumar Gala2011-07-11-13/+22
| | | | | | | | | | | Add ifdef protection for qp_info and liodn associated with Q/BMan. Also rearrange setting of _tbl_sz variables to utilize existing ifdef protection for things like FMAN. Also add protection around setup_portals() call in corenet_ds board code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix compile errors if CONFIG_SYS_{BR,OR}0_PRELIM aren't setKumar Gala2011-07-11-0/+2
| | | | | | | | Add ifdef protection in LBC code to handle the case in which CONFIG_SYS_BR0_PRELIM and CONFIG_SYS_OR0_PRELIM arent defined for a build. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC83XX: Fix PCI express clock setupBill Cook2011-07-06-2/+4
| | | | | | | | | | | | On a 8308 based board it was found that the PEX_GLK_RATIO register (programmed in arch/powerpc/cpu/mpc83xx/pcie.c) was getting set to 0, This was tracked to the fact that the pci express clock frequency was not being assigned to the pciexp1_clk entry in the global data structure in file arch/powerpc/cpu/mpc83xx/speed.c. Fix this and a similiar issue in 'do_clocks' command. Signed-off-by: Bill Cook <cook@isgchips.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* MPC83xx: add config options for memory setup.Andre Schwarz2011-07-06-1/+18
| | | | | | | | | CPO value and driver strength settings are board specifc. Also allow SPD data fetch from any accessible I2C EEPROM. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* MPC837x: set i2c1_clkAndre Schwarz2011-07-06-0/+2
| | | | | | | | | Running on mpc837x without CONFIG_FSL_ESDHC leads to i2c1_clk not being set at all. It is bound to clock of encryption module. fix this. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* powerpc/fsl_pci: Fix device tree fixups for newer platformsKumar Gala2011-05-20-1/+14
| | | | | | | | | | | | We assumed that only a small set of compatiable strings would be needed to find the PCIe device tree nodes to be fixed up. However on newer platforms the simple rules no longer work. We need to allow specifying the PCIe compatiable string for each individual SoC. We introduce CONFIG_SYS_FSL_PCIE_COMPAT for this purpose and set it if the default isn't sufficient. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Minor coding style cleanup.Wolfgang Denk2011-05-19-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* powerpc/mpc8xxx: reword max tCKmin messageYork Sun2011-05-13-3/+3
| | | | | | | | Reword "The DIMM max tCKmin is ..." to "The DDR clock is faster than the slowest DIMM(s) can support". Fixed interger type in printf as well. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: fix compatible property for the L2 cache nodeTimur Tabi2011-05-13-10/+19
| | | | | | | | | The compatible property for the L2 cache node (on 85xx systems that don't have a CPC) was using a value for the property length that did not match the actual length of the property. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* PPC405EX CHIP_21 erratumSteven A. Falco2011-05-12-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated 4/27/11) states that rev D processors may wake up with the wrong feature set. This patch implements the APM-proposed workaround. To enable this patch for your board, add the appropriate define for your CPU to your board header file. See kilauea.h for more information. The following variants are supported: #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY Please note that if you select the wrong define, your board will not boot, and JTAG will be required to recover. Tested on custom boards using: CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY <sfalco@harris.com> CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY <eibach@gdsys.de> Signed-off-by: Steve Falco <sfalco@harris.com> Acked-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2011-05-10-3/+1
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| * mpc83xx: restrict UTMI PHY configuration to 831x partsKim Phillips2011-04-04-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.e, to those parts that have PHY_CLK_VALID bits in their USB CONTROL registers: mpc8308 WU_INT, PHY_CLK_SEL, USB_EN, WU_INT_EN, ULPI_INT_EN mpc831x PHY_CLK_VALID, WU_INT, CLKIN_SEL, PHY_CLK_SEL, UTMI_PHY_EN, PLL_RESET, REFSEL, OTG_PORT, KEEP_OTG_ON, LSF_EN, USB_EN, ULPI_INT_EN mpc834x USB_EN, ULPI_INT1_EN (MPH only), ULPI_INT0_EN mpc837x USB_EN, ULPI_INT_EN (mpc832x, mpc8360 don't have a USB_EHCI_FSL compatible controller) this prevents non-831x parts from never completing cpu_init_f(), because the (non-existent) PHY_CLK_VALID bit never gets set. Reported-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Tested-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-04-30-57/+518
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| * | fsl-ddr: Fix mixed-case macro namesKyle Moffett2011-04-29-9/+9
| | | | | | | | | | | | | | | Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc: eSPI and eSPI controller supportMingkai Hu2011-04-29-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Singed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Cc: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Change timebase divisor to be defined per processorKumar Gala2011-04-28-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because different SoCs have different divisor amounts. All the PQ3 parts are /8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Implement work-around for P4080 erratum SERDES-A001Timur Tabi2011-04-28-16/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1 are swapped. Erratum SERDES-A001 says that if bank two is kept disabled and after bank three is enabled, then the PLL for bank three won't lock properly. The work-around is to enable and then disable bank two after bank three is enabled. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORATimur Tabi2011-04-28-17/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Display SERDES 8 erratum warning if banks are not disabledTimur Tabi2011-04-28-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | The work-around for P4080 erratum SERDES-8 requires all lanes of banks two and three to be disabled (powered down) in the RCW. Display a warning message if this is not the case. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005Timur Tabi2011-04-28-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Don't set FT_FSL_PCI_SETUP if CONFIG_PCI is not setMatthew McClintock2011-04-27-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A lot of boards set FT_FSL_PCI_SETUP directly in their board code and don't check to see if CONFIG_PCI is actually defined. This will cause the board compilation to fail if CONFIG_PCI is not defined. The p1022ds board is one such example. Instead of fixing every board this patch wraps FT_FSL_PCI_SETUP around CONFIG_PCI so we can remove CONFIG_PCI and boards will still build properly. Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: handle both "secX.Y" and "sec-vX.Y" propertiesKim Phillips2011-04-27-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | versioned SEC properties changed names during development, so for now search and update LIODNs for both "secX.Y" and "sec-vX.Y" based properties. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Enable ESDHC111 erratum on P2040/P3041/P5010/P5020 SoCsLei Xu2011-04-27-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The workaround for ESDHC111 should also be applied on P2040/P3041/P5010/P5020 SoCs. Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020Roy Zang2011-04-27-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)Kumar Gala2011-04-27-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | p4080/serdes: Implement the XAUI workaround for SERDES9 erratumEmil Medve2011-04-27-0/+116
| | | | | | | | | | | | | | | | | | Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: fsl_corenet_serdes code reworkEmil Medve2011-04-27-3/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework and add some new APIs to the fsl_corenet_serdes code for use by erratum and drivers. * Rename serdes_get_bank() to serdes_get_bank_by_lane() * Add serdes_get_first_lane returns which SERDES lane is used by device Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Add device tree fixup for bman portalHaiying Wang2011-04-27-1/+33
| | | | | | | | | | | | | | | | | | | | | Fix fdt bportal to pass the bman revision number to kernel via device tree. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdbRamneek Mehresh2011-04-27-0/+1
| | | | | | | | | | | | | | | | | | Second USB controller only works for SPI and SD boot because of pin muxing Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
| * | powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoCDipen Dudhat2011-04-27-0/+71
| | | | | | | | | | | | | | | Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: Change CS timing params before changing CS properties on IFCDipen Dudhat2011-04-27-16/+15
| | | | | | | | | | | | | | | | | | | | | | | | To make sure that machine change operation work successfully, change timing parameters first before changing machine for chip select on IFC. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-12-27 03:28:50 +0000