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* powerpc: P1025: Remove macro CONFIG_P1025York Sun2016-11-23-2/+2
| | | | | | | Replace CONFIG_P1025 with ARCH_P1025 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P1024: Remove CONFIG_P1024York Sun2016-11-23-1/+1
| | | | | | | Replace CONFIG_P1024 with ARCH_P1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P1021: Remove macro CONFIG_P1021York Sun2016-11-23-2/+2
| | | | | | | Replace CONFIG_P1021 with ARCH_P1021 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P1020: Remove macro CONFIG_P1020York Sun2016-11-23-1/+1
| | | | | | | Replace CONFIG_P1020 with ARCH_P1020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P1017: Drop configuration for P1017York Sun2016-11-23-20/+3
| | | | | | | P1017 is a single-core version of P1023. There is no P1017 target configured. Drop related macros. P1017 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P1014: Drop configuration for P1014York Sun2016-11-23-19/+2
| | | | | | | P1014 is a variant of P1010. There is no P1014 target configured. Drop related macros. P1014 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P1013: Drop configuration for P1013York Sun2016-11-23-18/+3
| | | | | | | P1013 is a single-core version of P1022. There is no P1022 target configured. Drop related macros. P1022 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P1012: Drop configuration for P1012York Sun2016-11-23-19/+1
| | | | | | | P1012 is a single-core version of P1021. There is no P1012 target configured. Drop related macros. P1012 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P1011: Remove macro CONFIG_P1011York Sun2016-11-23-1/+1
| | | | | | | Replace CONFIG_P1011 with ARCH_P1011 in Kconfig. P1011RDB seems to be in scrapyard though. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P1023: Remove macro CONFIG_P1023York Sun2016-11-23-4/+4
| | | | | | | Replace CONFIG_P1023 with ARCH_P1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P1022: Remove macro CONFIG_P1022York Sun2016-11-23-4/+4
| | | | | | | Replace CONFIG_P1022 with ARCH_P1022 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: P1010: Remove macro CONFIG_P1010York Sun2016-11-23-5/+5
| | | | | | | Replace CONFIG_P1010 with ARCH_P1010 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8572: Remove macro CONFIG_MPC8572York Sun2016-11-23-4/+4
| | | | | | | Replace CONFIG_MPC8572 with ARCH_MPC8572 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8569: Remove macro CONFIG_MPC8569York Sun2016-11-23-3/+3
| | | | | | | Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8568: Remove macro CONFIG_MPC8568York Sun2016-11-23-2/+2
| | | | | | | Replace CONFIG_MPC8568 with ARCH_MPC8568 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8560: Remove macro CONFIG_MPC8560York Sun2016-11-23-2/+2
| | | | | | | Replace CONFIG_MPC8560 with ARCH_MPC8560 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8555: Remove macro CONFIG_MPC8555York Sun2016-11-23-4/+4
| | | | | | | Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: mpc8541: Remove macro CONFIG_MPC8541York Sun2016-11-23-5/+5
| | | | | | | Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: mpc8540: Remove macro CONFIG_MPC8540York Sun2016-11-23-3/+3
| | | | | | | Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig optionYork Sun2016-11-23-4/+4
| | | | | | | Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: C29XPCIE: Remove macro CONFIG_C29XPCIEYork Sun2016-11-23-3/+3
| | | | | | Use CONFIG_TARGET_C29XPCIE instead. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig optionYork Sun2016-11-23-7/+7
| | | | | | | Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: BSC9132QDS: Remove CONFIG_BSC9132QDS macroYork Sun2016-11-23-2/+2
| | | | | | | Use CONFIG_TARGET_BSC9132QDS from Kconfig option, remove CONFIG_BSC9132QDS macro. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig optionsYork Sun2016-11-23-14/+14
| | | | | | | | | Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132 Kconfig options. Also drop #ifdef in BSC9131RDB.h since it is redundant. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8544: Move CONFIG_MPC8544 to Kconfig optionYork Sun2016-11-23-1/+1
| | | | | | Replace CONFIG_MPC8544 with ARCH_MPC8544 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig optionYork Sun2016-11-23-5/+5
| | | | | | Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com>
* mpc85xx: powerpc: usb: Update the list of Socs afftected by erratum A006261Sriram Dash2016-09-28-3/+1
| | | | | | | | | | | | | | | | | Apply the erratum A006261 for the following Socs: P2041 rev 2.0, P2040 rev 2.0, P5040 rev 2.0, 2.1 Do not apply erratum A006261 for the following Socs: T4160, T4080, T1040, T1042, T1020, T1022, T2080, T2081 Erratum A006261 is applicable for the following Socs: P1010(1.0, 2.0), P2041(1.0, 1.1, 2.0, 2.1), P2040(1.0, 1.1, 2.0, 2.1), P3041(1.0, 1.1, 2.0, 2.1), P5010(1.0, 2.0), P5020(1.0, 2.0), P5021(1.0, 2.0), T4240(1.0, 2.0), P5040(1.0,2.0,2.1). Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010Sriram Dash2016-09-28-0/+3
| | | | | | | | | CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy offset are set to enable the initial setting of Usb Phy for P1010. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-09-26-0/+4
|\ | | | | | | | | | | | | trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * fsl: serdes: ensure accessing the initialized maps of serdes protocolHou Zhiqiang2016-09-14-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Up to now, the function is_serdes_configed() doesn't check if the map of serdes protocol is initialized before accessing it. The function is_serdes_configed() will get wrong result when it was called before the serdes protocol maps initialized. As the first element of the map isn't used for any device, so use it as the flag to indicate if the map has been initialized. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Remove arch/${ARCH}/include/asm/errno.hMasahiro Yamada2016-09-23-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike Linux, nothing about errno.h is arch-specific in U-Boot. As you see, all of arch/${ARCH}/include/asm/errno.h is just a wrapper of <asm-generic/errno.h>. Actually, U-Boot does not export headers to user-space, so we just have to care about the consistency in the U-Boot tree. Now all of include directives for <asm/errno.h> are gone. Deprecate <asm/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
* | Convert CONFIG_SPL_DRIVERS_MISC_SUPPORT to KconfigSimon Glass2016-09-16-3/+0
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_HASH_SUPPORT to KconfigSimon Glass2016-09-16-1/+0
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Convert CONFIG_SPL_CRYPTO_SUPPORT to KconfigSimon Glass2016-09-16-1/+0
| | | | | | | | | | | | Move this option to Kconfig and tidy up existing uses. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Move existing use of CONFIG_SPL_RSA to KconfigSimon Glass2016-09-16-1/+0
| | | | | | | | | | | | | | A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Move existing use of CONFIG_SPL_DM to KconfigSimon Glass2016-09-16-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Note that quite a few boards defined this options but do not appear to actually use SPL: BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS_SPIFLASH_DDRCLK133_SECURE C29XPCIE_NOR_SECBOOT P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB-PA_NAND_SECBOOT P1010RDB-PA_NOR_SECBOOT P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB-PB_NAND_SECBOOT P1010RDB-PB_NOR_SECBOOT P3041DS_SECURE_BOOT P4080DS_SECURE_BOOT P5020DS_NAND_SECURE_BOOT P5040DS_SECURE_BOOT T1023RDB_SECURE_BOOT T1024QDS_DDR4_SECURE_BOOT T1024QDS_SECURE_BOOT T1024RDB_SECURE_BOOT T1040RDB_SECURE_BOOT T1042D4RDB_SECURE_BOOT T1042RDB_SECURE_BOOT T2080QDS_SECURE_BOOT T2080RDB_SECURE_BOOT T4160QDS_SECURE_BOOT T4240QDS_SECURE_BOOT ls1021aqds_nor_SECURE_BOOT ls1021atwr_nor_SECURE_BOOT ls1043ardb_SECURE_BOOT For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since they apparently don't have an SPL, this should not matter. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: fsl: Adjust ordering of #ifndef CONFIG_SPL_BUILDSimon Glass2016-09-16-1/+2
|/ | | | | | | | | | | | The secure boot header files incorrectly define SPL options only if CONFIG_SPL_BUILD is defined. This means that the options are only enabled in an SPL build, and not with a normal 'make xxx_defconfig'. This means that moveconfig.py cannot work, since it sees the options as disabled even when they may be manually enabled in an SPL build. Fix this by changing the order. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc/mpc85xx: Update erratum workaround for A006379York Sun2016-08-02-1/+1
| | | | | | | | Update erratum workaround for A006379 to set register CPCHDBCR0 with value 0x001e0000, replacing the old value 0x003c0000. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Dave Liu <dave.liu@nxp.com>
* SECURE_BOOT: Enable SD as a source for bootscriptSumit Garg2016-07-26-2/+2
| | | | | | | | | | | Add support for reading bootscript and bootscript header from SD. Also renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and NOR flash. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc/mpc85xx: T104x: Add nand secure boot targetSumit Garg2016-07-21-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPLSumit Garg2016-07-21-1/+30
| | | | | | | | | | | | | | | | As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-1/+1
| | | | | | | | | | | | | | | | | | | Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* dm: gpio: MPC85XX GPIO platform data supportHamish Martin2016-07-11-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a platform data structure for the MPC85XX GPIO driver to allow use of the driver without device tree. Users should define the GPIO blocks for their platform like this: struct mpc85xx_gpio_plat gpio_blocks[] = { { .addr = 0x130000, .ngpios = 32, }, { .addr = 0x131000, .ngpios = 32, }, }; U_BOOT_DEVICES(my_platform_gpios) = { { "gpio_mpc85xx", &gpio_blocks[0] }, { "gpio_mpc85xx", &gpio_blocks[1] }, }; This is intended to build upon the recent submission of the base MPC85XX driver from Mario Six. We need to use that new driver without dts support and this patch gives us that flexibility. This has been tested on a Freescale T2080 CPU, although only the first GPIO block. Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Reviewed-by: Mario Six <mario.six@gdsys.cc> Tested-by: Mario Six <mario.six@gdsys.cc> Acked-by: Simon Glass <sjg@chromium.org>
* dm: gpio: Add driver for MPC85XX GPIO controllermario.six@gdsys.cc2016-06-03-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well). Each GPIO bank is identified by its own entry in the device tree, i.e. gpio-controller@fc00 { #gpio-cells = <2>; compatible = "fsl,pq3-gpio"; reg = <0xfc00 0x100> } By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC). The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported. The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc: Drop unused code related to generic boardSimon Glass2016-05-27-104/+0
| | | | | | Since generic board init is enabled, this is not used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-05-24-0/+6
|\
| * arch/arm, arch/powerpc: add # of SEC engines on the SOCAlex Porosanu2016-05-18-0/+6
| | | | | | | | | | | | | | | | | | | | Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | dm: fsl_i2c: Enable DM for FSL I2Cmario.six@gdsys.cc2016-05-17-0/+10
| | | | | | | | Signed-off-by: Mario Six <mario.six@gdsys.cc>
* | dm: fsl_i2c: Rename I2C register structuremario.six@gdsys.cc2016-05-17-5/+5
|/ | | | Signed-off-by: Mario Six <mario.six@gdsys.cc>
* Kconfig: Move CONFIG_FIT and related options to KconfigSimon Glass2016-03-14-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-11-07 05:51:07 +0000