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| | * powerpc/mpc85xx: Update corenet global utility block registersYork Sun2013-05-14-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Add definitions for HDBCR registersAndy Fleming2013-05-14-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Makes it a bit easier to see if we've properly set them. While we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually use those definitions. Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Power: remove support for Freescale MPC8220Wolfgang Denk2013-05-15-260/+0
| |/ | | | | | | | | | | | | | | | | | | The Freescale MPC8220 Power Architecture processors have long reached EOL; Freescale does not even list these any more on their web site. Remove the code to avoid wasting maitaining efforts on dead stuff. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andy Fleming <afleming@gmail.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-0/+2
|\ \ | |/ |/| | | | | | | Conflicts: drivers/mtd/nand/mxc_nand_spl.c include/configs/m28evk.h
| * Add fsl_iim driverBenoît Thébaudeau2013-04-28-0/+2
| | | | | | | | | | | | Add a fsl_iim driver common to i.MX and MPC. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* | powerpc/mpc85xx: Extend workaround for erratum DDR_A003 to other SoCsYork Sun2013-05-02-0/+3
| | | | | | | | | | | | | | Erratum DDR_A003 applies to P5020, P3041, P4080, P3060, P2041, P5040. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc85xx:IFC Errata A003399 is not valid for BSC913xPrabhakar Kushwaha2013-05-02-2/+0
| | | | | | | | | | | | | | | | As per Errata list of BSC9131 and BSC9132, IFC Errata A003399 is no more valid. So donot compile its workaround. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0)Xulei2013-05-02-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | fman/mEMAC: set SETSP bit in IF_MODE regisgter for RGMII speedZang Roy-R619112013-05-02-0/+4
| | | | | | | | | | | | | | | | | | | | Some legacy RGMII phys don't have in band signaling for the speed information. so set the RGMII MAC mode according to the speed got from PHY. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Reported-by: John Traill <john.traill@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/b4860: Adding workaround errata A-005871Shengzhou Liu2013-05-02-0/+2
| | | | | | | | | | | | | | | | Per the latest errata updated, B4860/B4420 Rev 1.0 has also errata A-005871, so adding define A-005871 for B4 SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/b4: Fix the wrong register offset of B4 PCIE moduleLiu Gang2013-05-02-1/+2
|/ | | | | | | | | | | | B4420/B4860 PCIE can not work because of the wrong definition of the PCIE register offset in the file: arch/powerpc/include/asm/immap_85xx.h Add the judgement of B4420/B4860 to make the register offset to: #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* ppc: Enable generic board supportSimon Glass2013-03-15-0/+7
| | | | | | | This enables generic board support so that ppc boards can define CONFIG_SYS_GENERIC_BOARD. Signed-off-by: Simon Glass <sjg@chromium.org>
* Introduce generic link section.h symbol filesSimon Glass2013-03-15-0/+27
| | | | | | | | | | | | | | | | | | We create a separate header file for link symbols defined by the link scripts. It is helpful to have these all in one place and try to make them common across architectures. Since Linux already has a similar file, we bring this in even though many of the symbols there are not relevant to us. Each architecture has its own asm/sections.h where symbols specifc to that architecture can be added. For now everything except AVR32 just includes the generic header. One change is needed in arch/avr32/lib/board.c to make this conversion work. Reviewed-by: Tom Rini <trini@ti.com> (version 5) Signed-off-by: Simon Glass <sjg@chromium.org>
* Replace __bss_end__ with __bss_endSimon Glass2013-03-15-1/+1
| | | | | | | | | | | | | Note this is a tree-wide change affecting multiple architectures. At present we use __bss_start, but mostly __bss_end__. This seems inconsistent and in a number of places __bss_end is used instead. Change to use __bss_end for the BSS end symbol throughout U-Boot. This makes it possible to use the asm-generic/sections.h file on all archs. Signed-off-by: Simon Glass <sjg@chromium.org>
* mpc512x: Adjust the DRAM init sequence to the datasheet specAnatolij Gustschin2013-03-09-0/+1
| | | | | | | | Do maintain a 200 usecs period of stable power and clock before asserting the CKE signal and sending commands, have at least 200 DRAM clock cycles pass after initialization before data access. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* mpc512x: add ifm ac14xx boardAnatolij Gustschin2013-03-09-0/+13
| | | | | | | | Add new mpc5121e based ac14xx board and a new pinmux config function for setting individual pinmux bit groups. This function is used in ac14xx board code. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* mpc512x: allow configuring board specific IPS dividerAnatolij Gustschin2013-03-09-0/+2
| | | | | | | Boards may define own IPS divider in the config file if the default IPS divider doesn't fit their needs. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* mpc512x: optionally configure DIU, LPC and NFC devidersAnatolij Gustschin2013-03-09-0/+6
| | | | | | | If a board config file defines DIU, LPC and NFC deviders, configure them in the SCFR1 register. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* powerpc: Use generic global_dataSimon Glass2013-02-04-46/+1
| | | | | | Move powerpc over to use generic global_data. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: arm: Move sdhc_clk into arch_global_dataSimon Glass2013-02-04-3/+3
| | | | | | | This is used by both powerpc and arm, but I think it still qualifies as architecture-specific. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move kbd_status to arch_global_dataSimon Glass2013-02-04-3/+3
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move wdt_last to arch_global_dataSimon Glass2013-02-04-3/+3
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move fpga_state to arch_global_dataSimon Glass2013-02-04-3/+3
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Remove console_addr from global dataSimon Glass2013-02-04-6/+0
| | | | | | This does not appear to be used, so punt it. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move mirror_hack to arch_global_dataSimon Glass2013-02-04-3/+3
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Move uart_clk to arch_global_dataSimon Glass2013-02-04-3/+3
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move dp_alloc_base, dp_alloc_top to arch_global_dataSimon Glass2013-02-04-4/+4
| | | | | | Move these fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move arbiter fields to arch_global_dataSimon Glass2013-02-04-4/+4
| | | | | | | Move arbiter_event_attributes and arbiter_event_address into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move reset_status to arch_global_dataSimon Glass2013-02-04-1/+1
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move mpc8220 clocks to arch_global_dataSimon Glass2013-02-04-7/+6
| | | | | | | Move these fields into arch_global_data and tidy up. The bExtUart field does not appear to be used, so punt it. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move mpc512x clocks to arch_global_dataSimon Glass2013-02-04-4/+4
| | | | | | Move ips_clk and csb_clk into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move mpc5xxx clocks to arch_global_dataSimon Glass2013-02-04-3/+3
| | | | | | Move ipb_clk and pci_clk into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move used_tlb_cams to arch_global_dataSimon Glass2013-02-04-3/+3
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move used_laws to arch_global_dataSimon Glass2013-02-04-3/+3
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move CONFIG_QE to arch_global_dataSimon Glass2013-02-04-8/+6
| | | | | | Move the quantative easing fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: m68k: Move i2c1_clk, i2c2_clk to arch_global_dataSimon Glass2013-02-04-4/+5
| | | | | | | Move these fields into arch_global_data and tidy up. This is needed for both ppc and m68k since they share the i2c driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move lbc_clk and cpu to arch_global_dataSimon Glass2013-02-04-4/+4
| | | | | | | | Move these fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Update for bsc9132qds.c, b4860qds.c] Signed-off-by: Tom Rini <trini@ti.com>
* ppc: Move mpc83xx clock fields to arch_global_dataSimon Glass2013-02-01-39/+34
| | | | | | | Move al mpc83xx fields into arch_global_data and tidy up. Also indent the nested #ifdef for clarity. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move clock fields to arch_global_dataSimon Glass2013-02-01-0/+4
| | | | | | | | Move vco_out, cpm_clk, scc_clk, brg_clk into arch_global_data and tidy up. Leave pci_clk on its own since this should really depend only on CONFIG_PCI and not any particular chip type. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Remove extra pci_clk fields from global_dataSimon Glass2013-02-01-7/+2
| | | | | | | | | | | PPC has several of these fields, selected by chip type, although only one is ever compiled in. Instead, use a single field. It would be nice if this could be selected by CONFIG_PCI, but some chips (e.g. mpc5xxx) use pci_clk even when CONFIG_PCI is not enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move brg_clk to arch_global_dataSimon Glass2013-02-01-5/+9
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add architecture-specific global dataSimon Glass2013-02-01-0/+5
| | | | | | | | | | | | | We plan to move architecture-specific data into a separate structure so that we can make the rest of it common. As a first step, create struct arch_global_data to hold these fields. Initially it is empty. This patch applies to all archs at once. I can split it if this is really a pain. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc/t4240: Adding workaround errata A-005871Shengzhou Liu2013-01-30-0/+1
| | | | | | | | | | | | | | | When CoreNet Fabric (CCF) internal resources are consumed by the cores, inbound SRIO messaging traffic through RMan can put the device into a deadlock condition. This errata workaround forces internal resources to be reserved for upstream transactions. This ensures resources exist on the device for upstream transactions and removes the deadlock condition. The Workaround is for the T4240 silicon rev 1.0. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto'Vakul Garg2013-01-30-0/+7
| | | | | | | | | | If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: add support for MMUv2 page sizesScott Wood2013-01-30-18/+34
| | | | | | | | e6500 implements MMUv2 and supports power-of-2 page sizes rather than power-of-4. Add support for such pages. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Add BSC9132/BSC9232 processor supportPrabhakar Kushwaha2013-01-30-2/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:Add support of B4420 SoCPoonam Aggrwal2013-01-30-1/+22
| | | | | | | | | | | | | | | | | | | | | B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Few updates for B4860 cpu changesPoonam Aggrwal2013-01-30-1/+1
| | | | | | | | | | | | | | | - Added some more serdes1 and serdes2 combinations serdes1= 0x2c, 0x2d, 0x2e serdes2= 0x7a, 0x8d, 0x98 - Updated Number of DDR controllers to 2. - Added FMAN file for B4860, drivers/net/fm/b4860.c Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Add strcasecmp() and strncasecmp()Simon Glass2012-12-11-1/+1
| | | | | | | | | | | strncasecmp() is present as strnicmp() but disabled. Make it available and define strcasecmp() also. There is a only a small performance penalty to having strcasecmp() call strncasecmp(), so do this instead of a standalone function, to save code space. Update the prototype in arch-specific headers as needed to avoid warnings. Signed-off-by: Simon Glass <sjg@chromium.org>
* mpc5200: Add SPL supportStefan Roese2012-12-05-0/+31
| | | | | | | This patch adds SPL booting support (NOR flash) for the MPC5200 platforms. Signed-off-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-11-09 01:46:33 +0000