arm-boot/u-boot-imx.git - U-boot NXP imx6

	Commit message (Collapse)	Author	Age	Lines
*	powerpc/85xx: Add support for RMan LIODN initialization	Kumar Gala	2011-10-18	-0/+8
\| \| \| \| \| \| \| \| \|	This patch is intended to initialize RMan LIODN related registers on P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	powerpc/85xx: Update setting of SRIO LIODNs	Kumar Gala	2011-10-18	-0/+22
\| \| \| \| \| \| \| \| \| \| \|	Properly set the LIODN values associated with SRIO controller. On P4080/P3060 we have an LIODN per port and one for the RMU. On P2041/P3041/P5020 we have 2 LIODNs per port. Update the tables for all of these devices to properly handle both styles. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	powerpc/85xx: Add support for setting up RAID engine liodns on P5020	Kumar Gala	2011-10-03	-1/+10
\| \| \| \| \| \| \| \| \|	Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	powerpc/85xx: handle both "secX.Y" and "sec-vX.Y" properties	Kim Phillips	2011-04-27	-0/+13
\| \| \| \| \| \| \| \| \|	versioned SEC properties changed names during development, so for now search and update LIODNs for both "secX.Y" and "sec-vX.Y" based properties. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	powerpc/85xx: Fix setting of LIODN prop in PCIe nodes on P3041/P5020	Laurentiu TUDOR	2011-04-04	-2/+2
\| \| \| \| \| \| \| \| \| \| \| \| \|	We utilize the compatible string to find the node to add fsl,liodn property to. However P3041 & P5020 don't have "fsl,p4080-pcie" compatible for their PCIe controllers as they aren't backwards compatible. Allow the macro's to specify the PCIe compatible to use to allow SoC uniqueness. On P3041 & P5020 we utilize "fsl,qoriq-pcie-v2.2" for the PCIe controllers. Signed-off-by: Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs	Haiying Wang	2011-04-04	-5/+5
\| \| \| \| \| \| \| \| \| \| \| \| \| \|	There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs	Kumar Gala	2010-08-19	-4/+4
\| \| \| \| \| \| \| \|	Official docs call it the Job Ring not Job Queue for the p4080 security block. Match the docs to reduce confusion. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
*	powerpc/85xx: Add support to initialize LIODN registers and portals	Kumar Gala	2010-07-26	-0/+142
	On the new QorIQ/CoreNet based platforms we need to initialize the "portals" as access into the Data Path subystem as well as Logical IO Device Numbers (LIODN) that are used for the IOMMU (PAMU). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>