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* Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-07-24-29/+9
|\ | | | | | | | | | | | | | | | | | | | | The sandburst-specific i2c drivers have been deleted, conflict was just over the SPDX conversion. Conflicts: board/sandburst/common/ppc440gx_i2c.c board/sandburst/common/ppc440gx_i2c.h Signed-off-by: Tom Rini <trini@ti.com>
| * i2c, ppc4xx_i2c: switch to new multibus/multiadapter supportDirk Eibach2013-07-23-15/+5
| | | | | | | | | | | | | | Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Heiko Schocher <hs@denx.de> Cc: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
| * i2c, multibus: get rid of CONFIG_I2C_MUXHeiko Schocher2013-07-23-14/+0
| | | | | | | | | | | | | | | | | | | | | | CONFIG_I2C_MUX is replaced through the new i2c multibus/multiadapter framework, configured through CONFIG_SYS_I2C. As CONFIG_I2C_MUX is only used on the keymile boards, and they are now completely moved to the new framework, remove CONFIG_I2C_MUX. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Holger Brunck <holger.brunck@keymile.com> Tested-By: Holger Brunck <holger.brunck@keymile.com>
| * i2c: common changes for multibus/multiadapter supportHeiko Schocher2013-07-23-0/+4
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Cc: Henrik Nordström <henrik@henriknordstrom.net>
* | Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-3885/+240
|/ | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* powerpc/mpc85xx:Disable Debug TLB entry for non-minimal SPLPrabhakar Kushwaha2013-07-16-1/+3
| | | | | | | | | | CONFIG_SPL_BUILD creates debug TLB entry, so disable it before init_tlbs. CONFIG_SPL_INIT_MINIMAL never creates any debug TLB entry, so no need of disable_tlb(). Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: Add P1023RDB board supportChunhe Lan2013-06-20-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | P1023RDB Specification: ----------------------- Memory subsystem: 512MB DDR3 (Fixed DDR on board) 64MB NOR flash 128MB NAND flash Ethernet: eTSEC1: Connected to Atheros AR8035 GETH PHY eTSEC2: Connected to Atheros AR8035 GETH PHY PCIe: Three mini-PCIe slots USB: Two USB2.0 Type A ports I2C: AT24C08 8K Board EEPROM (8 bit address) Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:Disable Debug TLB entry before init_tlbsPrabhakar Kushwaha2013-06-20-0/+4
| | | | | | | | | init_tlbs() initialize all the TLB entries required for the system. So disable DEBUG TLB entry before TLB entries initialization. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc: mpc85xx/mpc86xx: Fix off-by-one boundary checking with ARRAY_SIZEAxel Lin2013-06-20-25/+25
| | | | | | | | If a variable is used as array subscript, it's valid value range is 0 ... ARRAY_SIZE -1. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: modify the functionality clear_bss and aligning the end ↵Ying Zhang2013-06-20-1/+3
| | | | | | | | | | | | | | | | | | | | address of the BSS There will clear the BSS in the function clear_bss(), the reset address of the BSS started from the __bss_start, and increased by four-byte increments, finally stoped depending on the address is equal to the _bss_end. If the end address __bss_end is not alignment to 4byte, it will be an infinite loop. 1. The reset action stoped depending on the reset address is greater than or equal the end address of the BSS. 2. The end address of the BSS should be 4byte aligned. Because the reset unit is 4 Bytes. This patch is on top of the patch "powerpc/mpc85xx: support application without resetvec segment in the linker script". Signed-off-by: Ying Zhang <b40530@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: support application without resetvec segment in the linker ↵Ying Zhang2013-06-20-0/+22
| | | | | | | | | | | | | | | | script For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM, then jump to it to begin execution. After that, the SPL loads the final uboot image into DDR, then jump to it to begin execution. The segment .resetvec in the SPL and in final U-boot is useless. So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application. If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded and the segment .bootpg is placed in the previous 4K of the segment .text. Signed-off-by: Ying Zhang <b40530@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: work around erratum A-006593Scott Wood2013-06-20-0/+6
| | | | | | | | | | | | Erratum A-006593 is "Atomic store may report failure but still allow the store data to be visible". The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit 21 to 1'b1. This may have a small impact on synthetic write bandwidth benchmarks but should have a negligible impact on real code." Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* fsl_ifc: add support for different IFC bank countMingkai Hu2013-06-20-1/+57
| | | | | | | | | | | | Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/boot: Change the macro of Boot from SRIO and PCIE master moduleLiu Gang2013-06-20-3/+3
| | | | | | | | | | | | | | | | | Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc: Use lower case for the core namesFabio Estevam2013-06-20-5/+5
| | | | | | | | | | | | | | | | | | Freescale documentation presents the PowerPC core names in lower case, such as "e300", "e500", "e600", etc. Change the upper case occurrences into lower case so that the core names reported in U-boot can match the ones from the documentation. While at it also fix a checkpatch error: ERROR: space prohibited before that close parenthesis ')' #53: FILE: arch/powerpc/cpu/mpc86xx/cpu.c:81: + printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); Reported-by: Heinz Wrobel <heinz.wrobel@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: new SPL support for IFC NANDPrabhakar Kushwaha2013-06-20-1/+1
| | | | | | | | | | | | | | Linker script is not able find start.o binary. So add its absolute path in u-boot-spl.lds. This change is similar to u-boot-nand.lds common/Makefile: Avoid compiling unnecssary files fsl_ifc_spl.c : It is is responsible for reading u-boot binary from NAND flash and copying into DDR. It also transfer control from NAND SPL to u-boot image present in DDR. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:No NOR boot, do not compile IFC errata A003399Prabhakar Kushwaha2013-06-20-4/+4
| | | | | | | | IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or no NOR boot, do not compile its workaround. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: explicit cast the SDRAM size to type phys_size_tMingkai Hu2013-06-20-1/+1
| | | | | | | | | | To avoid sign extension problem, use explicit casting to cast the SDRAM size to type phys_size_t, or else, if the SDRAM size is 2G(0x80000000), it will be extended to 0xffffffff80000000 when phys_size_t is type 'unsigned long long'. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Change clock-frequency compatible to 2.0Andy Fleming2013-06-20-1/+1
| | | | | | | | | Accidentally applied an earlier version of the patch, which set the compatible to "fsl,qoriq-clockgen-2", lacking the final ".0". Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
* powerpc: fix 8xx and 82xx type-punning warnings with GCC 4.7Scott Wood2013-06-11-13/+17
| | | | | | | | | | | C99's strict aliasing rules are insane to use in low-level code such as a bootloader, but as Wolfgang has rejected -fno-strict-aliasing in the past, add a union so that 16-bit accesses can be performed. Compile-tested only. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-30-5914/+592
|\ | | | | | | | | | | Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
| * powerpc/mpc85xx: Clear L1 D-cache lockYork Sun2013-05-24-0/+1
| | | | | | | | | | | | | | | | dcbi instruction has been used to clear D-cache lock. However, the cache lock is persistent for e6500 core. Use dcblc to clear the lock explicitly. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * SECURE BOOT - Removed deletion of TLB entries codeRuchika Gupta2013-05-24-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Boot ROM code creates TLB entries for 3.5G space before entering the u-boot. Earlier we were deleting these entries after early initialization of CPU. In recent past, code has been added to invalidate all these entries before relocation of u-boot code. So this code to delete TLB entries after CPU initialization is no longer required. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Acked-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Allow DDR overclockYork Sun2013-05-24-2/+0
| | | | | | | | | | | | | | | | | | | | Allow DDR clock runs faster than SPD specifes. This may cause memory failure, but the user should know what is going to happen when using higher than expected DDR clock. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/chassis2: Change core numbering schemeYork Sun2013-05-24-42/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Add T1040 and variant SoCsYork Sun2013-05-24-0/+237
| | | | | | | | | | | | | | | | | | T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Add e6500 L2 replacement policy selectionJames Yang2013-05-24-1/+2
| | | | | | | | | | | | | | This is compile-time config. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: check if core is disabled for showing statusYork Sun2013-05-24-0/+2
| | | | | | | | | | | | | | | | "cpu <num> status" should check if core is disabled before printing the spin table location. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Enable L2 cache parity/ECC error checkingJames Yang2013-05-24-2/+2
| | | | | | | | | | Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2013-05-15-92/+278
| |\
| | * powerpc/mpc8xxx: Allow board file to override DDR address assignmentYork Sun2013-05-14-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This gives boards flexibility to assign other than default addresses to each DDR controller. For example, DDR controler 2 can have 0 as the base and DDR controller 1 has higher memory. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Update workaround for DDR erratum A-004934York Sun2013-05-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The workaround has been updated to use a slightly different magic number. Change from 0x00003000 to 0x30003000. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.cRoy Zang2013-05-14-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY initialization can be reused in kernel without “usb start” command. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/85xx: add missing QMAN frequency calculationShaohui Xie2013-05-14-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not be initialized, and QMAN will have a wrong frequency display. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Add T4160 SoCYork Sun2013-05-14-0/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/t4240: Fix SerDes protocol arrays with const prefixYork Sun2013-05-14-7/+7
| | | | | | | | | | | | | | | | | | | | | Protocols are constants. Fix arrays with const prefix. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Fix PIR parsing for chassis2York Sun2013-05-14-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | The PIR parsing algorithm we used is not only for E6500. It applies to all SoCs with chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/corenet2: Print SerDes protocol in decimalYork Sun2013-05-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use decimal and hexadecimal for protocol numbers. It helps to match with SoC user manual. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Fix portal setupYork Sun2013-05-14-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Missing nodes of crypto, pme, etc in device tree is not a fatal error. Setting up the qman portal should skip the missing node and continue to finish the rest. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc8xxx: Fix DDR 3-way interleavingYork Sun2013-05-14-8/+11
| | | | | | | | | | | | | | | | | | | | | Should check if interleaving is enabled before using interleaving mode. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * T4/SerDes: correct the SATA indexRoy Zang2013-05-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Lane H on SerDes4 should be SATA2 instead of SATA1 Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * e6500: Move L1 enablement after L2 enablementAndy Fleming2013-05-14-47/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The L1 D-cache on e6500 is write-through. This means that it's not considered a good idea to have the L1 up and running if the L2 is disabled. We don't actually *use* the L1 until after the L2 is brought up on e6500, so go ahead and move the L1 enablement after that code is done. Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Add definitions for HDBCR registersAndy Fleming2013-05-14-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | Makes it a bit easier to see if we've properly set them. While we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually use those definitions. Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/B4860: Corrected FMAN1 operating frequency print at u-bootSandeep Singh2013-05-14-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | The bit positions for FMAN1 freq in RCW is different for B4860. Also addded a case when FMAN1 frewuency is equal to systembus. Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Power: remove support for Freescale MPC8220Wolfgang Denk2013-05-15-5770/+0
| |/ | | | | | | | | | | | | | | | | | | The Freescale MPC8220 Power Architecture processors have long reached EOL; Freescale does not even list these any more on their web site. Remove the code to avoid wasting maitaining efforts on dead stuff. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Andy Fleming <afleming@gmail.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-396/+1
|\ \ | |/ |/| | | | | | | Conflicts: drivers/mtd/nand/mxc_nand_spl.c include/configs/m28evk.h
| * mpc: iim: Switch to common fsl_iimBenoît Thébaudeau2013-04-28-396/+1
| | | | | | | | | | | | | | Make all mpc512x code point to the new common fsl_iim driver, and remove the former mpc512x-specific iim driver. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-05-02-41/+85
|\ \
| * | powerpc/mpc85xx: Changed LIODN offset valuesCristian Sovaiala2013-05-02-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extending LIODN offset range from 1-5 to 1-10 While using a qman portal with a higher index the LIODN offset is incorrectly set, thus extending the range of offsets covers all 10 qman portals Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Acked-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | powerpc/85xx: add SerDes bank 4 lanesTimur Tabi2013-05-02-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Only some chips have four SerDes banks, so don't define lanes for a bank that doesn't exist. Signed-off-by: Timur Tabi <timur@tabi.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit v1.1 at 2024-11-15 02:06:10 +0000