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* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-03-18-14/+14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Albert's rework of the linker scripts conflicted with Simon's making everyone use __bss_end. We also had a minor conflict over README.scrapyard being added to in mainline and enhanced in u-boot-arm/master with proper formatting. Conflicts: arch/arm/cpu/ixp/u-boot.lds arch/arm/cpu/u-boot.lds arch/arm/lib/Makefile board/actux1/u-boot.lds board/actux2/u-boot.lds board/actux3/u-boot.lds board/dvlhost/u-boot.lds board/freescale/mx31ads/u-boot.lds doc/README.scrapyard include/configs/tegra-common.h Build tested for all of ARM and run-time tested on am335x_evm. Signed-off-by: Tom Rini <trini@ti.com>
| * Refactor linker-generated arraysAlbert ARIBAUD2013-03-12-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor linker-generated array code so that symbols which were previously linker-generated are now compiler- generated. This causes relocation records of type R_ARM_ABS32 to become R_ARM_RELATIVE, which makes code which uses LGA able to run before relocation as well as after. Note: this affects more than ARM targets, as linker- lists span possibly all target architectures, notably PowerPC. Conflicts: arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds arch/arm/cpu/armv7/omap-common/u-boot-spl.lds board/ait/cam_enc_4xx/u-boot-spl.lds board/davinci/da8xxevm/u-boot-spl-da850evm.lds board/davinci/da8xxevm/u-boot-spl-hawk.lds board/vpac270/u-boot-spl.lds Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | Replace __bss_end__ with __bss_endSimon Glass2013-03-15-43/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | Note this is a tree-wide change affecting multiple architectures. At present we use __bss_start, but mostly __bss_end__. This seems inconsistent and in a number of places __bss_end is used instead. Change to use __bss_end for the BSS end symbol throughout U-Boot. This makes it possible to use the asm-generic/sections.h file on all archs. Signed-off-by: Simon Glass <sjg@chromium.org>
* | ppc: Remove PCIPPC2 and PCIPPC6 boardsStefan Roese2013-03-11-4/+3
| | | | | | | | | | | | | | | | | | | | These boards seem to be unmaintained for quite some time. So lets remove support for them completely. This also cleans up some common drivers/files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Guillaume Alexandre <guillaume.alexandre@gespac.ch> Acked-by: Wolfgang Denk <wd@denx.de>
* | mpc512x: Adjust the DRAM init sequence to the datasheet specAnatolij Gustschin2013-03-09-1/+16
| | | | | | | | | | | | | | | | Do maintain a 200 usecs period of stable power and clock before asserting the CKE signal and sending commands, have at least 200 DRAM clock cycles pass after initialization before data access. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | mpc512x: add ifm ac14xx boardAnatolij Gustschin2013-03-09-0/+54
| | | | | | | | | | | | | | | | Add new mpc5121e based ac14xx board and a new pinmux config function for setting individual pinmux bit groups. This function is used in ac14xx board code. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | mpc512x: optionally configure DIU, LPC and NFC devidersAnatolij Gustschin2013-03-09-0/+15
| | | | | | | | | | | | | | If a board config file defines DIU, LPC and NFC deviders, configure them in the SCFR1 register. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | mpc512x: use common code for clock setting for all mpc512x boardsAnatolij Gustschin2013-03-09-0/+9
| | | | | | | | | | | | | | | | | | Only define enabled clocks in the config file and enable the clocks in common code. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Cc: Wolfgang Denk <wd@denx.de>
* | mpc512x: add common LAW and Chip Select configurationAnatolij Gustschin2013-03-09-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently each mpc512x board has its own LAW and CS config code, we should avoid this code duplication. Allow all boards to use common code by only defining LAW and CS config macros like CONFIG_SYS_CSx_START, CONFIG_SYS_CSx_SIZE and CONFIG_SYS_CSx_CFG. Also allow common configuration of additional CS parameters by CONFIG_SYS_CS_ALETIMING, CONFIG_SYS_CS_BURST, CONFIG_SYS_CS_DEADCYCLE and CONFIG_SYS_CS_HOLDCYCLE options. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | mpc5200: spl_boot.c: Change init oder to first enable printfStefan Roese2013-03-09-6/+14
|/ | | | | | | | | | On MPC5200, the initial RAM (and gd) is located in the internal SRAM. So we can actually call the preloader console init code before calling initdram(). This makes serial output (printf) available very early, even before SDRAM init, which has been an U-Boot priciple from day 1. Signed-off-by: Stefan Roese <sr@denx.de>
* Clean up libfdt.h includesGerald Van Baren2013-02-08-4/+0
| | | | | | | | | | The libfdt.h file is the definition file for libfdt. It is unnecessary to include other fdt header files (the necessary ones are pulled in by libfdt.h). Signed-off-by: Gerald Van Baren <gvb@unssw.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Roese <sr@denx.de>
* common/fdt_support.c: sparse fixesKim Phillips2013-02-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | trivial: fdt_support.c:89:64: warning: Using plain integer as NULL pointer fdt_support.c:325:65: warning: Using plain integer as NULL pointer fdt_support.c:352:65: warning: Using plain integer as NULL pointer For the following bad constant expression, We hardcode the max. number of memory banks to four for the foreseeable future, and add an error with instructions on what to do once it's exceeded: fdt_support.c:397:22: error: bad constant expression For the rest below, sparse found a couple of wrong endian conversions in of_bus_default_translate() and fdt_get_base_address(), but otherwise the rest is mostly annotation fixes: fdt_support.c:64:24: warning: cast to restricted __be32 fdt_support.c:192:21: warning: incorrect type in assignment (different base types) fdt_support.c:192:21: expected unsigned int [unsigned] [usertype] tmp fdt_support.c:192:21: got restricted __be32 [usertype] <noident> fdt_support.c:201:21: warning: incorrect type in assignment (different base types) fdt_support.c:201:21: expected unsigned int [unsigned] [addressable] [usertype] tmp fdt_support.c:201:21: got restricted __be32 [usertype] <noident> fdt_support.c:304:13: warning: incorrect type in assignment (different base types) fdt_support.c:304:13: expected unsigned int [unsigned] [usertype] val fdt_support.c:304:13: got restricted __be32 [usertype] <noident> fdt_support.c:333:13: warning: incorrect type in assignment (different base types) fdt_support.c:333:13: expected unsigned int [unsigned] [usertype] val fdt_support.c:333:13: got restricted __be32 [usertype] <noident> fdt_support.c:359:13: warning: incorrect type in assignment (different base types) fdt_support.c:359:13: expected unsigned int [unsigned] [usertype] val fdt_support.c:359:13: got restricted __be32 [usertype] <noident> fdt_support.c:373:21: warning: cast to restricted __be32 fdt_support.c:963:48: warning: incorrect type in argument 1 (different base types) fdt_support.c:963:48: expected restricted __be32 const [usertype] *p fdt_support.c:963:48: got unsigned int [usertype] *<noident> fdt_support.c:971:48: warning: incorrect type in argument 1 (different base types) fdt_support.c:971:48: expected restricted __be32 const [usertype] *p fdt_support.c:971:48: got unsigned int [usertype] *<noident> fdt_support.c:984:29: warning: incorrect type in argument 1 (different base types) fdt_support.c:984:29: expected restricted __be32 const [usertype] *cell fdt_support.c:984:29: got unsigned int [usertype] *addr fdt_support.c:996:32: warning: incorrect type in argument 1 (different base types) fdt_support.c:996:32: expected restricted __be32 const [usertype] *cell fdt_support.c:996:32: got unsigned int [usertype] *addr fdt_support.c:1041:41: warning: incorrect type in argument 1 (different base types) fdt_support.c:1041:41: expected restricted __be32 const [usertype] *cell fdt_support.c:1041:41: got unsigned int [usertype] *addr fdt_support.c:1053:41: warning: incorrect type in argument 2 (different base types) fdt_support.c:1053:41: expected restricted __be32 const [usertype] *range fdt_support.c:1053:41: got unsigned int const [usertype] *[assigned] ranges fdt_support.c:1064:53: warning: incorrect type in argument 2 (different base types) fdt_support.c:1064:53: expected restricted __be32 const [usertype] *addr fdt_support.c:1064:53: got unsigned int [usertype] *addr fdt_support.c:1110:50: warning: incorrect type in argument 2 (different base types) fdt_support.c:1110:50: expected restricted __be32 const [usertype] *addr fdt_support.c:1110:50: got unsigned int *<noident> fdt_support.c:1121:49: warning: incorrect type in argument 1 (different base types) fdt_support.c:1121:49: expected restricted __be32 const [usertype] *cell fdt_support.c:1121:49: got unsigned int *<noident> fdt_support.c:1147:60: warning: incorrect type in argument 2 (different base types) fdt_support.c:1147:60: expected restricted __be32 const [usertype] *addr fdt_support.c:1147:60: got unsigned int *<noident> fdt_support.c:1081:5: warning: symbol '__of_translate_address' was not declared. Should it be static? fdt_support.c:1154:5: error: symbol 'fdt_translate_address' redeclared with different type (originally declared at include/fdt_support.h:95) - incompatible argument 3 (different base types) fdt_support.c: In function 'fdt_node_offset_by_compat_reg': fdt_support.c:1173:17: warning: initialization discards 'const' qualifier from pointer target type [enabled by default] See also linux kernel commit 0131d897 "of/address: use proper endianess in get_flags". Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Cc: Jerry Van Baren <gvb.uboot@gmail.com>
* ppc: arm: Move sdhc_clk into arch_global_dataSimon Glass2013-02-04-4/+5
| | | | | | | This is used by both powerpc and arm, but I think it still qualifies as architecture-specific. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Move uart_clk to arch_global_dataSimon Glass2013-02-04-4/+4
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move dp_alloc_base, dp_alloc_top to arch_global_dataSimon Glass2013-02-04-28/+30
| | | | | | Move these fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move arbiter fields to arch_global_dataSimon Glass2013-02-04-13/+15
| | | | | | | Move arbiter_event_attributes and arbiter_event_address into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move reset_status to arch_global_dataSimon Glass2013-02-04-6/+6
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move mpc8220 clocks to arch_global_dataSimon Glass2013-02-04-5/+7
| | | | | | | Move these fields into arch_global_data and tidy up. The bExtUart field does not appear to be used, so punt it. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move mpc512x clocks to arch_global_dataSimon Glass2013-02-04-10/+13
| | | | | | Move ips_clk and csb_clk into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move mpc5xxx clocks to arch_global_dataSimon Glass2013-02-04-13/+21
| | | | | | Move ipb_clk and pci_clk into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move used_tlb_cams to arch_global_dataSimon Glass2013-02-04-4/+4
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move used_laws to arch_global_dataSimon Glass2013-02-04-8/+8
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move CONFIG_QE to arch_global_dataSimon Glass2013-02-04-4/+5
| | | | | | Move the quantative easing fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: m68k: Move i2c1_clk, i2c2_clk to arch_global_dataSimon Glass2013-02-04-12/+14
| | | | | | | Move these fields into arch_global_data and tidy up. This is needed for both ppc and m68k since they share the i2c driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move lbc_clk and cpu to arch_global_dataSimon Glass2013-02-04-12/+12
| | | | | | | | Move these fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Update for bsc9132qds.c, b4860qds.c] Signed-off-by: Tom Rini <trini@ti.com>
* ppc: Move mpc83xx clock fields to arch_global_dataSimon Glass2013-02-01-37/+52
| | | | | | | Move al mpc83xx fields into arch_global_data and tidy up. Also indent the nested #ifdef for clarity. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move clock fields to arch_global_dataSimon Glass2013-02-01-12/+12
| | | | | | | | Move vco_out, cpm_clk, scc_clk, brg_clk into arch_global_data and tidy up. Leave pci_clk on its own since this should really depend only on CONFIG_PCI and not any particular chip type. Signed-off-by: Simon Glass <sjg@chromium.org>
* ppc: Move brg_clk to arch_global_dataSimon Glass2013-02-01-11/+12
| | | | | | Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc/t4240: Adding workaround errata A-005871Shengzhou Liu2013-01-30-0/+18
| | | | | | | | | | | | | | | When CoreNet Fabric (CCF) internal resources are consumed by the cores, inbound SRIO messaging traffic through RMan can put the device into a deadlock condition. This errata workaround forces internal resources to be reserved for upstream transactions. This ensures resources exist on the device for upstream transactions and removes the deadlock condition. The Workaround is for the T4240 silicon rev 1.0. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto'Vakul Garg2013-01-30-1/+85
| | | | | | | | | | If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mpc8xxx: fix DDR init value to use CONFIG_MEM_INIT_VALUEAnatolij Gustschin2013-01-30-0/+4
| | | | | | | | | | | Configuring custom memory init value using CONFIG_MEM_INIT_VALUE in the board config file doesn't work and memory is always initialized to the value 0xdeadbeef. Only use this default value if a board doesn't define CONFIG_MEM_INIT_VALUE. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Andy Fleming <afleming@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: add support for MMUv2 page sizesScott Wood2013-01-30-6/+15
| | | | | | | | e6500 implements MMUv2 and supports power-of-2 page sizes rather than power-of-4. Add support for such pages. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Add BSC9132/BSC9232 processor supportPrabhakar Kushwaha2013-01-30-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8xxxx: FSL DDR debugger auto run of stored commandsJames Yang2013-01-30-11/+47
| | | | | | | | | | | This patch adds the ability for the FSL DDR interactive debugger to automatically run the sequence of commands stored in the ddr_interactive environment variable. Commands are separated using ';'. ddr_interactive=compute; edit c0 d0 dimmparms caslat_X 0x3FC0; go Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Add copy command to FSL DDR interactiveJames Yang2013-01-30-0/+127
| | | | | | | | | Add copy command which allows copying of DIMM/controller settings. This saves tedious retyping of parameters for each identical DIMM or controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Fix data stage name matching issueJames Yang2013-01-30-1/+2
| | | | | | | | | | This fix allows the name of the stage to be specifed after the controler and DIMM is specified. Prior to this fix, if the data stage name is not the first entry on the command line, the operation is applied to all controller and DIMMs. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Move DDR command parsing to separate functionJames Yang2013-01-30-79/+74
| | | | | | | | Move the FSL DDR prompt command parsing to a separate function so that it can be reused. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8xxx: Enable entering DDR debugging by key pressYork Sun2013-01-30-2/+4
| | | | | | | | | | | | | | | Using environmental variable "ddr_interactive" to activate interactive DDR debugging seomtiems is not enough. For example, after updating SPD with a valid but wrong image, u-boot won't come up due to wrong DDR configuration. By enabling key press method, we can enter debug mode to have a chance to boot without using other tools to recover the board. CONFIG_FSL_DDR_INTERACTIVE needs to be defined in header file. To enter the debug mode by key press, press key 'd' shortly after reset, like one would do to abort auto booting. It is fixed to lower case 'd' at this moment. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:Fix Core cluster configuration loopPrabhakar Kushwaha2013-01-30-8/+22
| | | | | | | | | | | | | | Different personalities/derivatives of SoC may have reduced cluster. But it is not necessary for last valid DCFG_CCSR_TP_CLUSTER register to have DCFG_CCSR_TP_CLUSTER[EOC] bit set to represent "End of Clusters". EOC bit can still be set in last DCFG_CCSR_TP_CLUSTER register of orignal SoC which may not be valid for the personality. So add initiator type check to find valid cluster. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:Add support of B4420 SoCPoonam Aggrwal2013-01-30-0/+54
| | | | | | | | | | | | | | | | | | | | | B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Few updates for B4860 cpu changesPoonam Aggrwal2013-01-30-0/+15
| | | | | | | | | | | | | | | - Added some more serdes1 and serdes2 combinations serdes1= 0x2c, 0x2d, 0x2e serdes2= 0x7a, 0x8d, 0x98 - Updated Number of DDR controllers to 2. - Added FMAN file for B4860, drivers/net/fm/b4860.c Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Reserve default boot pageYork Sun2013-01-30-0/+16
| | | | | | | | | The boot page in memory is already reserved so OS won't overwrite. As long as the boot page translation is active, the default boot page also needs to be reserved in case the memory is 4GB or more. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc83xx: add support for new SPLScott Wood2012-12-19-12/+90
| | | | | | | | | | | | This adds arch support for PPC mpc83xx to boot "minimal" (4K) SPLs using the new infrastructure. Existing nand_spl targets are updated to deal with the name change from nand_init.c to spl_minimal.c (as in theory this isn't limited to NAND anymore). Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* env: Use getenv_yesno() more generallyJoe Hershberger2012-12-13-3/+1
| | | | | | | Move the getenv_yesno() to env_common.c and change most checks for 'y' or 'n' to use this helper. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* mpc5200: Add SPL supportStefan Roese2012-12-05-0/+162
| | | | | | | This patch adds SPL booting support (NOR flash) for the MPC5200 platforms. Signed-off-by: Stefan Roese <sr@denx.de>
* powerpc: Extract EPAPR_MAGIC constants into processor.hStefan Roese2012-12-05-1/+0
| | | | | | | | By extracting these defines into a header, they can be re-used by other C sources as well. This will be done by the SPL framework OS boot support. Signed-off-by: Stefan Roese <sr@denx.de>
* powerpc/mpc85xx: Fix a bug introduced by CONFIG_PPC_SPINTABLE_COMPATIBLEYork Sun2012-11-27-2/+2
| | | | | | | | | | | Fix a bug introduced by this patch powerpc/mpc85xx: Temporary fix for spin table backward compatibility Should have checked both CONFIG_PPC_SPINTABLE_COMPATIBLE and CONFIG_MP in cpu_init.c. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: update the work-around for P4080 erratum SERDES-9Timur Tabi2012-11-27-7/+13
| | | | | | | | | | The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p4080ds: fix PCI-e x8 link training down failureYuanquan Chen2012-11-27-0/+3
| | | | | | | | | | | | Due to SerDes configuration error, if we set the PCI-e controller link width as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to PCI-e slot, it fails to train down to the PCI-e device's link width. According to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between RC and EP. Signed-off-by: Yuanquan Chen <B41889@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: implement check for erratum A-004580 work-aroundTimur Tabi2012-11-27-0/+48
| | | | | | | | | | | | | | | | | | | The work-around for erratum A-004580 ("Internal tracking loop can falsely lock causing unrecoverable bit errors") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004580, we can do this by verifying that the values in the specific registers that the work-around says to update. This change requires access to the SerDes lane sub-structure in serdes_corenet_t, so we make it a named struct. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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