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* powerpc/p4080: Fix warning in serdes code from early use of hwconfigYork Sun2011-01-19-3/+14
| | | | | | | Hwconfig is called before relocating. Use the new hwconfig APIs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Implement workaround for erratum DDR-A003York Sun2011-01-19-1/+83
| | | | | | | | Erratum DDR-A003 requires workaround to correctly set RCW10 for registered DIMM. Also adding polling after enabling DDR controller to ensure completion. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Enable unique mode registers and dynamic ODT for DDR3York Sun2011-01-19-54/+512
| | | | | | | | | | | | | | | | | | Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version (major, minor, errata) to determine if unique mode registers are available. If true, always use unique mode registers. Dynamic ODT is enabled if needed. The table is documented in doc/README.fsl-ddr. This function may also need to be extend for future other platforms if such a feature exists. Enable address parity and RCW by default for RDIMMs. Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for quad-rank RDIMMs. Use a formula to calculate rodt_on for timing_cfg_5. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Adding more registers and optionsYork Sun2011-01-19-3/+9
| | | | | | | | | | | | | This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8xxx: Enable ECC on/off control in hwconfigYork Sun2011-01-19-3/+6
| | | | | | | | | | | | | | Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file, ECC can be turned on/off by this switch. If this switch is omitted, it is ON by default. Updated hwconfig calls to use local buffer. Syntax is hwconfig=fsl_ddr:ecc=on Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8xxx: Display RDIMM if detectedYork Sun2011-01-19-12/+8
| | | | | | | Print a message when a RDIMM is detected. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Add hwconfig APIs to address early parsing used by DDR initKumar Gala2011-01-19-19/+59
| | | | | | | | | | | | | | | | | | | | | | | | | There are several users of the hwconfig APIs (8xxx DDR) before we have the environment properly setup. This causes issues because of the numerous ways the environment might be accessed because of the non-volatile memory it might be stored in. Additionally the access might be so early that memory isn't even properly setup for us. Towards resolving these issues we provide versions of all the hwconfig APIs that can be passed in a buffer to parse and leave it to the caller to determine how to allocate and populate the buffer. We use the _f naming convention for these new APIs even though they are perfectly useable after relocation and the environment being ready. We also now warn if the non-f APIs are called before the environment is ready to allow users to address the issues. Finally, we convert the 8xxx DDR code to utilize the new APIs to hopefully address the issue once and for all. We have the 8xxx DDR code create a buffer on the stack and populate it via getenv_f(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* powerpc/p2040: Add various p2040 specific informationKumar Gala2011-01-19-0/+68
| | | | | | | | | | Add P2040 SoC specific information: * SERDES Table * Added p2040 to cpu_type_list and SVR list * Added number of LAWs for p2040 * Set CONFIG_MAX_CPUS to 4 for p2040 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p5020: Add various p5020 specific informationKumar Gala2011-01-19-0/+258
| | | | | | | | | Add P5020 SoC specific information: * SERDES Table * LIODN setup * Portal configuration Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p3041: Add various p3041 specific informationKumar Gala2011-01-19-0/+258
| | | | | | | | | Add P3041 SoC specific information: * SERDES Table * LIODN setup * Portal configuration Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add Support for Freescale P1014 ProcessorPoonam Aggrwal2011-01-19-0/+3
| | | | | | | | | | | | The P1014 is similar to the P1010 processor with the following differences: - 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC) - no eCAN interface. (P1010 has 2 eCAN interfaces) - Two SGMII interface (P1010 has 3 SGMII) - No secure boot Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add Support for Freescale P1010 ProcessorPoonam Aggrwal2011-01-19-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Key Features include of the P1010: * e500v2 core frequency operation of 500 to 800 MHz * Power consumption less than 5.0 W at 800 MHz core speed * Dual SATA 3 Gbps controllers with integrated PHY * Dual PCI Express controllers * Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs) * TCP/IP acceleration and classification capabilities * IEEE 1588 support * Lossless flow control * RGMII, SGMII * DDR3 with support for a 32-bit data interface (40 bits including ECC), up to 800 MHz data rate 32/16-bit DDR3 memory controller * Dedicated security engine featuring trusted boot * TDM interface * Dual controller area networks (FlexCAN) controller * SD/MMC card controller supporting booting from Flash cards * USB 2.0 host and device controller with an on-chip, high-speed PHY * Integrated Flash controller (IFC) * Power Management Controller (PMC) * Four-channel, general-purpose DMA controller * I2C controller * Serial peripheral interface (SPI) controller with master and slave support * System timers including a periodic interrupt timer, real-time clock, software watchdog timer, and four general-purpose timers * Dual DUARTs Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Move RESET_VECTOR_ADDRESS into config.hKumar Gala2011-01-19-2/+6
| | | | | | | | | | | Rather than defining it config.mk we can set it in config.h and remove config.mk from several boards that don't need it. We mimic what 4xx does and introduce CONFIG_RESET_VECTOR_ADDRESS for config.h to set. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* 8xxx/ddr: add support to only compute the ddr sdram sizeHaiying Wang2011-01-19-9/+40
| | | | | | | | | This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in case that the DDR SDRAM is initialized in the 2nd stage uboot and should not be intialized again in the final stage uboot. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080)Kumar Gala2011-01-14-1/+9
| | | | | | | | | Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus monitor timeout. Set timeout to maximum to avoid. Based on a patch from Lan Chunhe <b25806@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080)Kumar Gala2011-01-14-0/+6
| | | | | | | CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080)Kumar Gala2011-01-14-0/+8
| | | | | | | CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr codeKumar Gala2011-01-14-1/+21
| | | | | | | | Move the parsing of hwconfig to determine if to use spd into common code so we can share it across all boards instead of duplicating it everywhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)Roy Zang2011-01-14-0/+11
| | | | | | | | | | False multi-bit ECC errors will be reported by the eSDHC buffer which can trigger a reset request. We disable all ECC error checking on SDHC. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)Roy Zang2011-01-14-0/+3
| | | | | | | | | | | The default value of the SRS, VS18 and VS30 and ADMAS fields in the host controller capabilities register (HOSTCAPBLT) are incorrect. The default of these bits should be zero instead of one. Clear these bits out when we read HOSTCAPBLT. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080)Jerry Huang2011-01-14-1/+4
| | | | | | | | | Do not issue a manual asynchronous CMD12. Instead, use a (software) synchronous CMD12 or AUTOCMD12 to abort data transfer. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/86xx: Enable common SRIO init codeKumar Gala2011-01-14-2/+12
| | | | | | | | Add the needed defines and code to utilize the common 8xxx srio init code to setup LAWs and modify device tree if we have SRIO enabled on a board. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Refactor SRIO initialization into common codeKumar Gala2011-01-14-3/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved the SRIO init out of corenet_ds and into common code for 8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe controllers for SRIO. We utilize the fact that SRIO is over serdes to determine if its configured or not and thus can setup the LAWs needed for it dynamically. We additionally update the device tree (to remove the SRIO nodes) if the board doesn't have SRIO enabled. Introduced the following standard defines for board config.h: CONFIG_SYS_SRIO - Chip has SRIO or not CONFIG_SRIO1 - Board has SRIO 1 port available CONFIG_SRIO2 - Board has SRIO 2 port available (where 'n' is the port #) CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup) CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup) [ These mimic what we have for PCI and PCIe controllers ] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* powerpc/85xx: Fix bug in dcache_disableKumar Gala2011-01-14-2/+2
| | | | | | | | We set the L1 dache register with a bogus register value. Need to be using 'r3' instead of 'r0'. Reported-by: John Traill <john.traill@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC8xxx DDR: align informational printsBecky Bruce2011-01-14-2/+3
| | | | | | | | | | | | | | | | | | | | Add spaces to cause the informational prints to line up with the ones from init_func_ram() in board.c. Output now looks like this: .... DRAM: Detected 4096 MB of memory This U-Boot only supports < 4G of DDR You could rebuild it with CONFIG_PHYS_64BIT DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC off) .... The prints from lbc_sdram_init() have also been modified to line line up and changed to start with "LBC SDRAM" instead of the confusing "SDRAM". Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx boards: Rename CONFIG_DDR_DLL to CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_INBecky Bruce2011-01-14-1/+4
| | | | | | | | | This config option is for an erratum workaround; rename it to be more clear. Also, drop it from config files don't need it and were undefining it. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: rename sdram_init() lbc_sdram_init()Becky Bruce2011-01-14-3/+3
| | | | | | | | sdram_init() is used to initialize sdram on the lbc. Rename it accordingly. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx boards: initdram() cleanup/bugfixBecky Bruce2011-01-14-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences: 1) DDR tlbs for the fixed_sdram case were set up in initdram() on some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner. 2) Parts that require the DDR11 erratum workaround had different implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad. The xpedite boards had a common/fsl_8xxx_ddr.c; with this change only the 517 board uses this so I have moved the ddr code into that board's directory in xpedite517x.c Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx/tlb.c: Allow platforms to specify wimge bitsBecky Bruce2011-01-14-1/+5
| | | | | | | | | | | | | Some platforms might want to override the default wimge=0 for DDR. Add CONFIG_SYS_PPC_DDR_WIMGE for those platforms to use. This will initially only be used by TQM85xx, but could be useful for other boards or testing going forward. Note that the name of this define is not 85xx-specific. WIMGE is a fairly universal concept, so any ppc platforms that require different WIMGE settings for DDR can use the same #define. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Replace is_fsl_pci_cfg with is_serdes_configuredKumar Gala2011-01-14-205/+0
| | | | | | | Now that we have serdes support for all 85xx/86xx/Pxxx chips we can replace the is_fsl_pci_cfg() code with the is_serdes_configured(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add is_serdes_configured() support for P1021 SERDESKumar Gala2011-01-14-0/+68
| | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add is_serdes_configured() support for MPC8544 SERDESKumar Gala2011-01-14-0/+96
| | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add is_serdes_configured() support for MPC8569 SERDESKumar Gala2011-01-14-0/+75
| | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add is_serdes_configured() support for MPC8568 SERDESKumar Gala2011-01-14-0/+66
| | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add is_serdes_configured() support for MPC8548 SERDESKumar Gala2011-01-14-0/+66
| | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add is_serdes_configured() support for MPC8572 SERDESKumar Gala2011-01-14-0/+82
| | | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Chenhui Zhao <b26998@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add is_serdes_configured() support for P2020 SERDESKumar Gala2011-01-14-0/+75
| | | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/86xx: Add SERDES support on MPC8641 & MPC8610Kumar Gala2011-01-14-1/+186
| | | | | | | | | Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. This mimics the code we have in place for the 85xx platforms. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Create a SERDES section in MakefileKumar Gala2011-01-14-2/+5
| | | | | | | Created a section in the Makefile for SoC specific SERDES code. Also added P1013 SERDES (use P1022 SERDES code). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Replace CONFIG_SYS_HAS_SERDES with a weak functionKumar Gala2011-01-14-2/+6
| | | | | | Instead of a #define use a null weak function for fsl_serdes_init Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc4xx: Fix compilation breakage in miiphy.cStefan Roese2011-01-11-1/+1
| | | | | | | | Patch 8ef583a0 [miiphy: convert to linux/mii.h] introduced a small problem in the ppc4xx miiphy.c version. This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
* miiphy: convert to linux/mii.hMike Frysinger2011-01-09-38/+38
| | | | | | | | The include/miiphy.h header duplicates a lot of things from linux/mii.h. So punt all the things that overlap to keep the API simple and to make merging between U-Boot and Linux simpler. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* 74xx_7xx/mpc86xx/ppmc7xx: Fix do_reset() declarationPeter Tyser2010-12-17-5/+10
| | | | | | | | | | | | | | | | | The following commit: commit 882b7d726febe65579d6502c271412ecb05821d7 Author: Mike Frysinger <vapier@gentoo.org> Date: Wed Oct 20 03:41:17 2010 -0400 do_reset: unify duplicate prototypes missed the 74xx_7xx and mpc86xx arches and the ppmc7xx board do_reset() functions which resulted in build errors such as: cpu.c:128: error: conflicting types for 'do_reset' include/command.h:102: error: previous declaration of 'do_reset' was here Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* PowerPC: Add relocation support for -fpicJoakim Tjernlund2010-12-17-22/+33
| | | | | | | | | By rearranging the linker script we get support for relocation of -fpic for free. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Scott Wood <scottwood@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* xilinx-ppc4xx-generic: Use common u-boot.ldsRicardo Ribalda Delgado2010-12-17-1/+9
| | | | | | | Use common ppc4xx linker script for xilinx ppc440 and ppc405 related boards. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Clarify comment about boot chip-select in start.SStefan Roese2010-12-17-12/+14
| | | | | | | Ths old comment was quite screwed up. Replace it with a new version that should be a bit more descriptive. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of ../master into nextWolfgang Denk2010-12-16-7/+15
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| * mpc83xx: fix pcie enumerationBaidu Boy2010-12-13-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | This patch fix a problem for the pcie enumeration for mpc83xx cpus. Without this we will not get correct value in hose->regions[...]. The pointer *reg in function mpc83xx_pcie_init_bus() shall not be changed. Because we will use this pointer as a parameter to call function mpc83xx_pcie_register_hose(). Signed-off-by: Baidu Boy <liucai.lfn@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * powerpc/85xx: do not reloc l2srbar if CONFIG_FLASH_BASE is not definedHaiying Wang2010-12-01-1/+1
| | | | | | | | | | | | | | | | This fixes the compiling error for the board which doesn't have NOR flash (so CONFIG_FLASH_BASE is not defined) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc83xx: Make it boot againJoakim Tjernlund2010-11-30-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | After the removal of COLD/WARM start flags my mpc8321 board didn't boot anymore. Trial and error suggests that map/remap_flash_by_xxx needs to wait after updating LBLAWAR1 to make sure the the change has reached the HW before continuing with the code that depends on it. Final fix suggested by Scott Wood. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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