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* powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slotsYork Sun2011-09-29-4/+7
| | | | | | | The two slots on the same controller have different addresses. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_enYork Sun2011-09-29-9/+10
| | | | | | | | Check second DIMM slot in case the first one is empty. Honor DQS enable option for SDRAM mode register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Move DDR RCW overriding to common codeYork Sun2011-09-29-0/+15
| | | | | | | | DDR RCW varies at different speeds. It is common for all platform. Move it out from corenet_ds. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Extend CWL tableYork Sun2011-09-29-2/+16
| | | | | | | Extend CAS write Latency (CWL) table to comply with DDR3 spec Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536Kumar Gala2011-09-29-3/+0
| | | | | | | | The MPC8536 seems to use only 3 bits for the major revision field in the SVR rather than the 4 bits used by all other processors. The most significant bit is used as a mfg code on MPC8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support for FMan ethernet in Independent modeKumar Gala2011-09-29-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mp: add support for discontiguous coresTimur Tabi2011-09-29-25/+56
| | | | | | | | | | Some SOCs have discontiguously-numbered cores, and so we can't determine the valid core numbers via the FRR register any more. We define CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions to process the mask and enumerate over the set of valid cores. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fdt: Rename fdt_create_phandle to fdt_set_phandleKumar Gala2011-09-29-1/+1
| | | | | | | | The old fdt_create_phandle didn't actually create a phandle it just set one. We'll introduce a new helper that actually does creation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
* powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't setKumar Gala2011-09-29-1/+8
| | | | | | | | Add ifdef protection around fman specific code related to device tree clock setup. If we dont have CONFIG_SYS_DPAA_FMAN defined we shouldn't be executing this code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)Poonam Aggrwal2011-09-29-0/+93
| | | | | | | | | | | | | | | | | | Issue: Address masking doesn't work properly. When sum of the base address, defined by BA, and memory bank size, defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask CSPRn[BA] bits. Impact: This will impact booting when we are reprogramming CSPR0(BA) and AMASK0(AMASK) while executing from NOR Flash. Workaround: Re-programming of CSPR(BA) and AMASK is done while not executing from NOR Flash. The code which programs the BA and AMASK is executed from L2-SRAM. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)Poonam Aggrwal2011-09-29-0/+15
| | | | | | | | | | | | | | | Issue: Peripheral connected to IFC_CS3 may hamper booting from IFC. Impact: Boot from IFC may not be successful if IFC_CS3 is used. Workaround: If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR. Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)Poonam Aggrwal2011-09-29-0/+3
| | | | | | | | | | | | | | | Issue: The NOR-FCM does not support access to unaligned addresses for 16 bit port size Impact: When 16 bit port size is used, accesses not aligned to 16 bit address boundary will result in incorrect data Workaround: The workaround is to switch to GPCM mode for NOR Flash access. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1MPoonam Aggrwal2011-09-29-3/+4
| | | | | | | | | | | For an IFC Erratum (A-003399) we will need to access IFC registers in cpu_init_early_f() so expand the TLB covering CCSR to 1M. Since we need a TLB to cover 1M we move to using TLB1 array for all the early mappings so we can cover various sizes beyond 4k. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* nand: Freescale Integrated Flash Controller NAND supportDipen Dudhat2011-09-29-3/+25
| | | | | | | | | | | | | | | Add NAND support (including spl) on IFC, such as is found on the p1010. Note that using hardware ECC on IFC with small-page NAND (which is what comes on the p1010rdb reference board) means there will be insufficient OOB space for JFFS2, since IFC does not support 1-bit ECC. UBI should work, as it does not use OOB for anything but ECC. When hardware ECC is not enabled in CSOR, software ECC is now used. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> [scottwood@freescale.com: ECC rework and misc fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
* powerpc/85xx: relocate CCSR before creating the initial RAM areaTimur Tabi2011-09-29-58/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before main memory (DDR) is initialized, the on-chip L1 cache is used as a memory area for the stack and the global data (gd_t) structure. This is called the initial RAM area, or initram. The L1 cache is locked and the TLBs point to a non-existent address (so that there's no chance it will overlap main memory or any device). The L1 cache is also configured not to write out to memory or the L2 cache, so everything stays in the L1 cache. One of the things we might do while running out of initram is relocate CCSR. On reset, CCSR is typically located at some high 32-bit address, like 0xfe000000, and this may not be the best place for CCSR. For example, on 36-bit systems, CCSR is relocated to 0xffe000000, near the top of 36-bit memory space. On some future Freescale SOCs, the L1 cache will be forced to write to the backing store, so we can no longer have the TLBs point to non-existent address. Instead, we will point the TLBs to an unused area in CCSR. In order for this technique to work, CCSR needs to be relocated before the initram memory is enabled. Unlike the original CCSR relocation code in cpu_init_early_f(), the TLBs we create now for relocating CCSR are deleted after the relocation is finished. cpu_init_early_f() will still need to create a TLB for CCSR (at the new location) for normal U-Boot purposes. This is done to keep the impact to existing U-Boot code minimal and to better isolate the CCSR relocation code. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc4xx: Flush dcache after DDR2 autocalibration with caches onStefan Roese2011-09-19-0/+7
| | | | | | | | Flush the dcache before removing the TLB with caches enabled. Otherwise this might lead to problems later on, e.g. while booting Linux (as seen on ICON-440SPe). Signed-off-by: Stefan Roese <sr@denx.de>
* Convert ISO-8859 files to UTF-8Albert ARIBAUD2011-08-04-1/+1
| | | | | | | | There was a mix of UTF-8 and ISO-8859 files in the U-Boot source tree, which could cause issues with the patchwork review system. This commit converts all ISO-8859 files to UTF-8. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* video: Add SHARP LQ084S3LG01 LCD support on P1022DSTimur Tabi2011-08-04-1/+1
| | | | | | | | | | | | | | | | | The SHARP LQ084S3LG01 is a TFT LCD used on the P1022DS (revision "C") board. This device only supports 800x600 resolution, so if that resolution is selected, assume that this is the device. The device is attached to the LVDS port on the P1022DS board. The existing 800x600 entry (for the PDM360NG board) is actually 800x480, so we fix that. To support two different 800x resolutions, the Y-resolution is now passed to fsl_diu_init() and both values are used to pick the proper fb_videomode structure. The data for the 800x600 video mode is originally from Jiang Yutang. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Jiang Yutang <b14898@freescale.com>
* powerpc/8xxx: Remove dependency on <usb.h>Kumar Gala2011-07-29-4/+3
| | | | | | | | | | | | | | | We used <usb.h> for USB_MAX_DEVICE. However this requires we actual build in support for USB into u-boot (which should not be required for device tree fixup). At this time no FSL SoC that utilizies this code (83xx/85xx) has more than 2 USB controllers. So we replace USB_MAX_DEVICE with a local define FSL_MAX_NUM_USB_CTRLS. If/when a device shows up with more than 2 controllers we can easily bump this value or refactor into a proper define per SoC. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: enable USB2 gadget mode for corenet ds boardShaohui Xie2011-07-29-2/+0
| | | | | | | | | | to make USB2 worked in gadget mode, we need to set it's 'dr_mode' to 'peripheral' in hwconfig, but driver starts scan from 'usb1', it'll break out if it cannot find 'usb1', so drop the 'else' clause to make driver scan all the 'usbx'. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: verify the device tree before booting LinuxTimur Tabi2011-07-29-0/+72
| | | | | | | | | | | | | | | Introduce ft_verify_fdt(), a function that is called after the device tree has been fixed up, that displays warning messages if there is a mismatch between the physical addresses of some devices that U-Boot has configured with what the device tree says the addresses are. This is a particular problem when booting a 36-bit device tree from a 32-bit U-Boot (or vice versa), because the physical address of CCSR is wrong in the device tree. When the operating system boots, no messages are displayed, so the user generally has no idea what's wrong. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC8xxx: drop redundant boot messagesWolfgang Denk2011-07-29-1/+1
| | | | | | | | | | | | | | | Current code would print RAM size information like this: DRAM: DDR: 256 MiB (DDR1, 64-bit, CL=2, ECC off) Turn a number of printf()s into debug() to get rid of the redundant "DDR: " string like this: DRAM: 256 MiB (DDR1, 64-bit, CL=2, ECC off) Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Cleanup handling of PVR detection for e500/e500mc/e5500Kumar Gala2011-07-29-19/+13
| | | | | | | | At some point we broke the detection of e500v1 class cores. Fix that and simply the code to just utilize PVR_VER() to have a single case statement. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix up clock_freq property in CAN node of dtsBhaskar Upadhaya2011-07-29-0/+3
| | | | | | | | | Fix up the device tree property associated with the Flexcan clock frequency. This property is used to calculate the bit timing parameters for Flexcan. Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: provide 85xx flush_icache for cmd_cacheMatthew McClintock2011-07-29-0/+2
| | | | | | | | This provides a function that will override the weak function flush_icache to let 85xx boards to flush the icache cc: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Matthew McClintock <msm@freescale.com>
* powerpc/85xx: Handle the lack of L2 cache on P2040/P2040EKumar Gala2011-07-29-9/+37
| | | | | | | | | | The P2040/P2040E have no L2 cache. So we utilize the SVR to determine if we are one of these devices and skip the L2 init code in cpu_init.c and release. For the device tree we skip the updating of the L2 cache properties but we still update the chain of caches so the CPC/L3 node can be properly updated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support for P2041[e] XAUI in SERDESKumar Gala2011-07-29-5/+21
| | | | | | | | | | | | | | | We add XAUI_FM1 into the SERDES tables for P2041[e] devices. However for the P2040[e] devices that dont support XAUI we handle this at runtime via SVR checks. If we are on a P2040[e] device the SERDES functions will behave as follows: is_serdes_prtcl_valid() will always report invalid if prtcl passed in is XAUI_FM1. serdes_get_prtcl() will report NONE if the prtcl in the table is set to XAUI_FM1. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rename P2040 id & SERDES to P2041Kumar Gala2011-07-29-3/+3
| | | | | | | | P2041 is the superset part that covers both P2040 & P2041. The only difference between the two devices is that P2041 supports 10g/XAUI and has an L2 cache. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Adding configuration for DCSRCR to enable 32M accessStephen George2011-07-29-0/+11
| | | | | | | | | | | | | | | Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* unify version_stringAndreas Bießmann2011-07-28-97/+18
| | | | | | | | | | | | This patch removes the architecture specific implementation of version_string where possible. Some architectures use a special place and therefore we provide U_BOOT_VERSION_STRING definition and a common weak symbol version_string. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> CC: Mike Frysinger <vapier@gentoo.org> CC: Peter Pan <pppeterpppan@gmail.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* serial: drop useless ctlr fieldMike Frysinger2011-07-26-13/+8
| | | | | | | | | | | | | | | | | | | The multi serial support has a "ctlr" field which almost no one uses, but everyone is forced to set to useless strings. So punt it. Funny enough, the only code that actually reads this field (the mpc8xx driver) has a typo where it meant to look for the SCC driver. Fix it while converting the check to use the name field. Signed-off-by: Mike Frysinger <vapier@gentoo.org> CC: Heiko Schocher <hs@denx.de> CC: Anatolij Gustschin <agust@denx.de> CC: Tom Rix <Tom.Rix@windriver.com> CC: Minkyu Kang <mk7.kang@samsung.com> CC: Craig Nauman <cnauman@diagraph.com> CC: Marek Vasut <marek.vasut@gmail.com> CC: Prafulla Wadaskar <prafulla@marvell.com> CC: Mahavir Jain <mjain@marvell.com>
* serial: push default_serial_console to driversMike Frysinger2011-07-26-0/+28
| | | | | | | | | | | | | | | | | Rather than sticking arch/board/driver specific logic in the common serial code, push it all out to the respective drivers. The serial drivers declare these funcs weak so that boards can still override things with their own definition. Signed-off-by: Mike Frysinger <vapier@gentoo.org> CC: Heiko Schocher <hs@denx.de> CC: Anatolij Gustschin <agust@denx.de> CC: Tom Rix <Tom.Rix@windriver.com> CC: Minkyu Kang <mk7.kang@samsung.com> CC: Craig Nauman <cnauman@diagraph.com> CC: Prafulla Wadaskar <prafulla@marvell.com> CC: Mahavir Jain <mjain@marvell.com> Tested-by: Minkyu Kang <mk7.kang@samsung.com>
* powerpc/mpc85xx: Add clear_ddr_tlbs functionBecky Bruce2011-07-22-11/+32
| | | | | | | | | | | This is useful when we just want to wipe out the TLBs. There's currently a function that resets the ddr tlbs to a different value; it is changed to utilize this function. The new function can be used in conjunction with setup_ddr_tlbs() for a board to temporarily map/unmap the DDR address range as needed. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fman: insert the Fman firmware into the device treeTimur Tabi2011-07-22-0/+123
| | | | | | | | | | | | The Fman device tree node binding allows for the entire Fman firmware binary data to be embedded in the device tree. This eliminates the need to have NOR flash mapped to Linux just so that the Fman driver can see the firmware. The location of the Fman firmware is taken from the 'fman_ucode' environment variable. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: add support the ePAPR "phandle" propertyTimur Tabi2011-07-22-2/+4
| | | | | | | | | | | The ePAPR specification says that phandle properties should be called "phandle", and not "linux,phandle". To facilitate the migration from "linux,phandle" to "phandle", we update fdt_qportal() to use the new function, fdt_create_phandle(). This function abstracts the creation of phandle properties. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix detection of P1017EKumar Gala2011-07-17-1/+1
| | | | | | Had a typo such that P1017E would not be detected correctly. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: remove SERDES4 soft-reset work-aroundTimur Tabi2011-07-11-22/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some P4080 rev1 errata work-arounds, notably erratum SERDES4, required a bank soft-reset after the bank was configured and enabled, even though enabling a bank causes it to reset. Because the reset was required for multiple errata, it was not properly enclosed in an #ifdef, and so was not removed with all the other rev1 errata work-arounds. Erratum SERDES-8 says that the clocks for bank 3 needs to be enabled if bank 2 is enabled, but this was not being done for SERDES protocols 0xF and 0x10. The bank reset also happened to enable bank 3 (apparently an undocumented feature). Simply removing the reset breaks these two protocols. It turns out that every time we call enable_bank(), we do want at least one lane of the bank enabled, either because the bank is supposed to be enabled, or because we need the clock from that bank enabled. For erratum SERDES-A001, we don't want to modify srds_lpd_b[] when we call enable_bank(), because that array is used elsewhere to determine if the bank is available. Note that the side effect of these changes is that the work-arounds for these two errata are now linked. Specifically, if SERDES-A001 is enabled, then we need SERDES-8 enabled as well. Because this was the only SERDES bank soft-reset, there is no need to implement a work-around for erratum SERDES-A003. Also fix an off-by-one error in a printf(). Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Ed Swarthout <swarthou@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Allow override DDR read-to-write turnaround timeYork Sun2011-07-11-0/+3
| | | | | | | Add this option to allow boards to override the default read-to-write turnaround time for better performance. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/8xxx: Update USB mode device tree fixupRamneek Mehresh2011-07-11-12/+65
| | | | | | | | | | | | Modify support for USB mode fixup: - Add common support for USB mode and phy type device tree fix-up for all USB controllers mentioned in hwconfig string - Fetch USB mode and phy type via hwconfig; if not defined in hwconfig, then fetch them from env Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: fix DDR data width checkingYork Sun2011-07-11-8/+27
| | | | | | | | | Checking width before setting DDR controller. SPD for DDR1 and DDR2 has data width and primary sdram width. The latter one has different meaning for DDR3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Adding fallback to raw timing on supported boardsYork Sun2011-07-11-0/+8
| | | | | | | | In case of empty SPD or checksum error, fallback to raw timing on supported boards. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Enable calculation for fixed DDR chipsYork Sun2011-07-11-3/+33
| | | | | | | | | | We used to have fixed parameters for soldered DDR chips. This patch introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing data from DDR chip datasheet, implemneted in board-specific files or header files. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Add 16-bit support for DDR3York Sun2011-07-11-2/+15
| | | | | | | | Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit DDR devices. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: check SPD length before using part numberYork Sun2011-07-11-1/+2
| | | | | | | | Only use DDR DIMM part number if SPD has valid length, to prevent from display garbage in case SPD doesn't cover these fields. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: adjust DDR burst length and chop accroding to sdram widthYork Sun2011-07-11-4/+20
| | | | | | | | If the bus width is 32-bit, burst chop should be disabled and burst length should be 8. Read from SPD or other source to determine the width. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add P2041 processor supportKumar Gala2011-07-11-0/+8
| | | | | | The P2041 is similar to P2040, however has a 10G port and backside L2 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p2040: Add various p2040 specific informationMingkai Hu2011-07-11-0/+133
| | | | | | | | | | | Add P2040 SoC specific information: * LIODN setup * Portal configuration * etc Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix compile errors if CONFIG_SYS_DPAA_QBMAN isn't setKumar Gala2011-07-11-13/+22
| | | | | | | | | | | Add ifdef protection for qp_info and liodn associated with Q/BMan. Also rearrange setting of _tbl_sz variables to utilize existing ifdef protection for things like FMAN. Also add protection around setup_portals() call in corenet_ds board code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix compile errors if CONFIG_SYS_{BR,OR}0_PRELIM aren't setKumar Gala2011-07-11-0/+2
| | | | | | | | Add ifdef protection in LBC code to handle the case in which CONFIG_SYS_BR0_PRELIM and CONFIG_SYS_OR0_PRELIM arent defined for a build. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC83XX: Fix PCI express clock setupBill Cook2011-07-06-2/+4
| | | | | | | | | | | | On a 8308 based board it was found that the PEX_GLK_RATIO register (programmed in arch/powerpc/cpu/mpc83xx/pcie.c) was getting set to 0, This was tracked to the fact that the pci express clock frequency was not being assigned to the pciexp1_clk entry in the global data structure in file arch/powerpc/cpu/mpc83xx/speed.c. Fix this and a similiar issue in 'do_clocks' command. Signed-off-by: Bill Cook <cook@isgchips.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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