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* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2012-09-25-782/+1160
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| * powerpc/85xx: clear out TLB on bootScott Wood2012-08-23-33/+43
| | | | | | | | | | | | | | | | Instead of just shooting down the entry that covers CCSR, clear out every TLB entry that isn't the one that we're executing out of. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Move HWCONFIG_BUFFER_SIZE into config.hYork Sun2012-08-23-5/+0
| | | | | | | | | | | | | | | | | | | | Before proper environment is setup, we extract hwconfig and put it into a buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to accommodate longer string. Since this macro is used in multiple files, we move it into arch/powerpc/include/asm/config.h. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx DDR: Fix interactive DDR debuggingYork Sun2012-08-23-2/+2
| | | | | | | | | | | | | | | | Add one more argument to call function readline_into_buffer(). Fix print SPD format for negative values. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx DDR: Fall back to raw timing for first controller onlyYork Sun2012-08-23-1/+1
| | | | | | | | | | | | | | | | Only the first DIMM of first controller should fall back to raw timing parameters if SPD is missing or corrupted. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx DDR: Fix CAS latency calculationYork Sun2012-08-23-2/+4
| | | | | | | | | | | | | | Empty slot should be skipped when calculating CAS latency. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Fix bug for extended DDR timingYork Sun2012-08-23-20/+43
| | | | | | | | | | | | | | | | Faster DDR3 timing requires parameters exceeding previously defined range. Extended parameters are fixed. Added some debug messages. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleavingYork Sun2012-08-23-317/+434
| | | | | | | | | | | | | | | | Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Add support for cas latency 12 and aboveYork Sun2012-08-23-7/+21
| | | | | | | | | | | | | | | | Required by JEDEC 79-3E for high speed DDR3. Also change "CSn disabled" message to debug. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Add fine timing support for DDR3York Sun2012-08-23-12/+35
| | | | | | | | | | | | | | | | When the DDR3 speed goes higher, we need to utilize fine offset from SPD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Skip zero values for DDR debug registersYork Sun2012-08-23-3/+11
| | | | | | | | | | | | | | | | | | | | | | Some debug registers have non-zero default out of reset. If software is not setting debug registers, skip writing to them to avoid unnecessary overriding. Also add debug messages for workarounds and debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: fix core id for multicore bootingYork Sun2012-08-23-6/+47
| | | | | | | | | | | | | | | | | | | | For the cores with multiple threads, we need to figure out which physical core a thread belongs. To match the core ids, update PIR registers and spin tables. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Added new ext fields to IFCKumar Gala2012-08-23-0/+12
| | | | | | | | | | | | | | | | | | | | In case more than 32 bit address is used, the EXT bit should be set. Need to fix up address map for IFC #CS for 4, also need to move # of IFC banks into config_mpc85xx.h Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Add e6500 processor detectionKumar Gala2012-08-23-0/+3
| | | | | | | | | | Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: use topology registers to calculate number of coresYork Sun2012-08-23-9/+56
| | | | | | | | | | | | | | | | | | We have actual topology infomation to find out exactly which core is present. Calculate the number of cores if not specified. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/fsl-corenet: work around erratum A004510Scott Wood2012-08-23-0/+314
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A004510 says that under certain load conditions, modified cache lines can be discarded, causing data corruption. To work around this, several CCSR and DCSR register updates need to be made in a careful manner, so that there is no other transaction in corenet when the update is made. The update is made from a locked cacheline, with a delay before to flush any previous activity, and a delay after to flush the CCSR/DCSR update. We can't use a readback because that would be another corenet transaction, which is not allowed. We lock the subsequent cacheline to prevent it from being fetched while we're executing the previous cacheline. It is filled with nops so that a branch doesn't cause us to fetch another cacheline. Ordinarily we are running in a cache-inhibited mapping at this point, so we temporarily change that. We make it guarded so that we should never see a speculative load, and we never do an explicit load. Thus, only the I-cache should ever fill from this mapping, and we flush/unlock it afterward. Thus we should avoid problems from any potential cache aliasing between inhibited and non-inhibited mappings. NOTE that if PAMU is used with this patch, it will need to use a dedicated LAW as described in the erratum. This is the responsibility of the OS that sets up PAMU. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/fsl-corenet: remove dead variant symbolsScott Wood2012-08-23-3/+0
| | | | | | | | | | | | | | | | | | | | | | These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: remove support for the Freescale P3060Timur Tabi2012-08-23-240/+1
| | | | | | | | | | | | | | | | The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx: add support for FM2 DTSEC5Timur Tabi2012-08-23-0/+6
| | | | | | | | | | | | | | | | Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc8xxx: Remove P1015 and P1016 from CPU listYork Sun2012-08-23-8/+1
| | | | | | | | | | | | | | | | P1015 is the same as P1011 and P1016 is the same as P1012 from software point of view. They have different packages but share SVRs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/corenet_ds: Master module for boot from PCIELiu Gang2012-08-23-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2" or "PCIE3" using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build targetLiu Gang2012-08-23-94/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of the SRIOBOOT_MASTER build target, and to support for serving as a SRIO boot master via environment variable. Set the environment variable "bootmaster" to "SRIO1" or "SRIO2" using the following command: setenv bootmaster SRIO1 saveenv The "bootmaster" will enable the function of the SRIO boot master, and this has the following advantages compared with SRIOBOOT_MASTER build configuration: 1. Reduce a build configuration item in boards.cfg file. No longer need to build a special image for master, just use a normal target image and set the "bootmaster" variable. 2. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just set the corresponding value to "bootmaster" based on the using SRIO port. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditionalYork Sun2012-08-23-3/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This erratum applies to the following SoCs: P4080 rev 1.0, 2.0, fixed in rev 3.0 P2041 rev 1.0, 1.1, fixed in rev 2.0 P3041 rev 1.0, 1.1, fixed in rev 2.0. Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround may degrade performance. P4080 erratum CPU22 shares the same workaround. So it is always enabled for P4080. For other SoCs, it can be disabled by hwconfig with syntax: fsl_cpu_a011:disable Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * mpc85xx: Initial SP alignment is wrong.Joakim Tjernlund2012-08-22-11/+5
| | | | | | | | | | | | | | | | | | | | | | | | PowerPC mandates SP to be 16 bytes aligned. Furthermore, a stack frame is added, pointing to the reset vector which may in the way when gdb is walking the stack because the reset vector may not accessible depending on emulator settings. Also use a temp register so gdb doesn't pick up intermediate values. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | mpc5xxx: add GPIO port configurationAnatolij Gustschin2012-09-01-0/+14
|/ | | | | | | Add posibility for board specifig GPIO configurations using various CONFIG_SYS_ macros. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNsTimur Tabi2012-08-08-14/+14
| | | | | | | | | | The SET_PCI_LIODN() macro takes a compatible property string as a parameter, so that it knows which PCI device tree node to look for. The calls to these macros are using a hard-coded string, but we already have the CONFIG_SYS_FSL_PCIE_COMPAT macro which contains the same string, so we should use that. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/ddr: fix fsl_ddr_get_dimm_params compile errorShaohui Xie2012-08-08-1/+1
| | | | | | | | | | fsl_ddr_get_dimm_params() should be wrapped by CONFIG_SYS_DDR_RAW_TIMING, otherwise, when using fixed_sdram() instead of using SPD, it will cause compile error. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GBYork Sun2012-08-08-2/+11
| | | | | | | | | The fix for errata workaround is to avoid covering physical address 0xff000000 to 0xffffffff during the implementation. Early commit eb672e92 works until DDR size exceeds 4GB. This fix works for DDR size up to 64GB. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'next' of git://git.denx.de/u-bootWolfgang Denk2012-07-30-1/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://git.denx.de/u-boot: MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c doc: cleanup - move board READMEs into respective board directories net: sh_eth: add support for SH7757's GETHER net: sh_eth: modify the definitions of regsiter net: sh_eth: add SH_ETH_TYPE_ condition net: sh_eth: clean up for the SH7757's code net: fec_mxc: Fix MDC for xMII net: fec_mxc: Fix setting of RCR for xMII net: nfs: make NFS_TIMEOUT configurable net: Inline the new eth_setenv_enetaddr_by_index function net: allow setting env enetaddr from net device setting net/designware: Consecutive writes to the same register to be avoided CACHE: net: asix: Fix asix driver to work with data cache on net: phy: micrel: make ksz9021 phy accessible net: abort network initialization if the PHY driver fails phylib: phy_startup() should return an error code on failure net: tftp: fix type of block arg to store_block Signed-off-by: Wolfgang Denk <wd@denx.de>
| * MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.cMarek Vasut2012-07-30-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpu.c: In function ‘check_CPU’: cpu.c:256:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Subject slightly changed. Signed-off-by: Wolfgang Denk <wd@denx.de> Tested on TQM855MDCBAB7-T66.102 (MPC855T at 66 MHz) and TQM860LDB0A3-T50.202 (MPC860T at 50MHz). Tested-by: Wolfgang Denk <wd@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* | MPC83xx, MPC85xx: compile stub cache functionStefano Babic2012-07-21-2/+2
|/ | | | | | | | | | | | | | | | | An empty flush_dcache_range() was added into MPC83xx and MPC85xx to work with drivers shared with other architecture. However, it is compiled only if USB is set, but it is required for other drivers (FSL_ESDHC), too. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Andy Fleming <afleming@gmail.com> CC: Dirk Behme <dirk.behme@de.bosch.com> CC: Marek Vasut <marex@denx.de> CC: Wolfgang Denk <wd@denx.de> Added MPC83xx version. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2012-07-08-110/+180
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040E powerpc/mpc85xx: Workaround for erratum CPU_A011 powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER() powerpc/P4080: Check SVR for CPU22 workaround lib/powerpc: addrmap_phys_to_virt() should return a pointer powerpc/85xx: clean up P1022DS board configuration header file powerpc/85xx: fdt_set_phy_handle() should return an error code powerpc/85xx: minor clean-ups to the P2020DS board header file powerpc/p1010rdb: add readme document for p1010rdb powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting powerpc/mpc85xx:Add debugger support for e500v2 SoC powerpc/85xx:Fix NAND code base to support debugger powerpc/85xx:Make debug exception vector accessible powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger PATCH 1/4][v4] doc:Add documentation for e500 external debugger support powerpc/p1010rdb: update mux config of p1010rdb board powerpc/mpc85xx:Add BSC9131 RDB Support powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support powerpc/85xx: Add USB device-tree fixup for various platforms Signed-off-by: Wolfgang Denk <wd@denx.de>
| * powerpc/mpc85xx: Fix Handling the lack of L2 cache on P2040/P2040EYork Sun2012-07-06-7/+4
| | | | | | | | | | | | Fix SVR checking for commit acf3f8da. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Workaround for erratum CPU_A011York Sun2012-07-06-10/+36
| | | | | | | | | | | | | | | | | | Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0. It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the same workaround as erratum CPU22. Rearrange registers usage in assembly code to avoid accidental overwriting. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()York Sun2012-07-06-60/+11
| | | | | | | | | | | | | | | | We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER(). This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with encryption. Remove all _E entries from SVR list and CPU list. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/P4080: Check SVR for CPU22 workaroundYork Sun2012-07-06-4/+15
| | | | | | | | | | | | Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only. Signed-off-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address settingPrabhakar Kushwaha2012-07-06-26/+0
| | | | | | | | | | | | | | | | | | | | During NAND_SPL boot, base address and different register are programmed default by corresponding NAND controllers(eLBC/IFC). These settings are sufficient enough for NAND SPL. Avoid updating these register.They will be programmed during NAND RAMBOOT. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * powerpc/85xx:Fix NAND code base to support debuggerPrabhakar Kushwaha2012-07-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR + IVOR15 should be valid fetchable OP code address. As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to any fetchable valid data Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * powerpc/85xx:Make debug exception vector accessiblePrabhakar Kushwaha2012-07-06-6/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR + IVOR15) to have valid and fetchable OP code. 1) While executing in translated space (AS=1), whenever a debug exception is generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to fetch an instruction from the debug exception vector (IVPR + IVOR15); since now we are in AS=0, the application needs to ensure the proper TLB configuration to have (IVOR + IVOR15) accessible from AS=0 also. Create a temporary TLB in AS0 to make sure debug exception verctor is accessible on debug exception. 2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * powerpc/85xx:Fix MSR[DE] bit in MSR to support debuggerPrabhakar Kushwaha2012-07-06-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Debugging of e500 and e500v1 processer requires MSR[DE] bit to be set always. Where MSR = Machine State register Make sure of MSR[DE] bit is set uniformaly across the different execution address space i.e. AS0 and AS1. Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Catalin Udma <catalin.udma@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
| * powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor SupportPrabhakar Kushwaha2012-07-06-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - BSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. - BSC9130 is exactly same as BSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131). - BSC9231 is similar to BSC9131 except no MAPLE The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. This patch takes care of code pertaining to power side functionality only. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc/mpc83xx: fix copyright string in serdes.cTimur Tabi2012-07-03-1/+1
|/ | | | | | | | The misspelling of "semiconductor" causes some internal copyright analysis tools to complain. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* MPC8xxx: Define cache ops for USBMarek Vasut2012-06-07-0/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch conditionally defines flush_dcache_range() and invalidate_dcache_range() on MPC8xxx, to avoid EHCI complaining, resulting in the following output: $ ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- ./MAKEALL MPC8572DS Configuring for MPC8572DS board... make: *** [u-boot] Error 1 powerpc-linux-gnu-size: './u-boot': No such file e1000.c: In function ‘e1000_initialize’: e1000.c:5264:13: warning: assignment from incompatible pointer type [enabled by default] tsec.c: In function ‘tsec_initialize’: tsec.c:638:12: warning: assignment from incompatible pointer type [enabled by default] drivers/usb/host/libusb_host.o: In function `ehci_td_buffer': /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:186: undefined reference to `flush_dcache_range' drivers/usb/host/libusb_host.o: In function `ehci_submit_async': /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:346: undefined reference to `flush_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:348: undefined reference to `flush_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:349: undefined reference to `flush_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:372: undefined reference to `invalidate_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:374: undefined reference to `invalidate_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:376: undefined reference to `invalidate_dcache_range' /home/marex/U-Boot/u-boot-imx/drivers/usb/host/ehci-hcd.c:386: undefined reference to `invalidate_dcache_range' make: *** [u-boot] Error 1 --------------------- SUMMARY ---------------------------- Boards compiled: 1 Boards with errors: 1 ( MPC8572DS ) ---------------------------------------------------------- Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Anatolij Gustschin <agust@denx.de>
* net: cosmetic: Un-typedef Ethernet_tJoe Hershberger2012-05-23-9/+8
| | | | | | | Separate the Ethernet header from the 802 header. Base the size constants on the structs. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* net: Encapsulate CDP packet identificationJoe Hershberger2012-05-23-1/+1
| | | | | | Checking for CDP packets should be encapsulated, not copied code. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* arch/powerpc/cpu/mpc8260/ether_scc.c: Fix compile warningJoe Hershberger2012-05-22-1/+1
| | | | | | | | Fix this: ether_scc.c: In function 'mpc82xx_scc_enet_initialize': ether_scc.c:377:14: warning: assignment from incompatible pointer type Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* arch/powerpc/cpu/mpc85xx/ether_fcc.c: Fix compile warningJoe Hershberger2012-05-22-1/+1
| | | | | | | | Fix this: ether_fcc.c: In function 'fec_initialize': ether_fcc.c:453:15: warning: assignment from incompatible pointer type Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* arch/powerpc/cpu/mpc8260/ether_fcc.c: Fix compile warningJoe Hershberger2012-05-22-1/+1
| | | | | | | | Fix this: ether_fcc.c: In function 'fec_initialize': ether_fcc.c:390:15: warning: assignment from incompatible pointer type Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* arch/powerpc/cpu/mpc8220/fec.c: Fix compile warningJoe Hershberger2012-05-22-3/+2
| | | | | | | | | | | Fix this: fec.c: In function 'mpc8220_fec_recv': fec.c:791:9: warning: passing argument 1 of 'NetReceive' discards qualifiers from pointer target type include/net.h:438:13: note: expected 'uchar *' but argument is of type 'volatile uchar *' fec.c: In function 'mpc8220_fec_initialize': fec.c:839:12: warning: assignment from incompatible pointer type Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* MPC8xx: fix "Remove volatile from net API" aftermathWolfgang Denk2012-05-22-5/+5
| | | | | | | | | | | | | | | | | Commit db288a9 "net: Remove volatile from net API" caused a number of build warnings: fec.c: In function 'fec_initialize': fec.c:183:13: warning: assignment from incompatible pointer type [enabled by default] fec.c: In function 'fec_recv': fec.c:284:5: warning: passing argument 1 of 'NetReceive' discards 'volatile' qualifier from pointer target type [enabled by default] /home/wd/git/u-boot/work/include/net.h:433:13: note: expected 'uchar *' but argument is of type 'volatile uchar *' scc.c: In function 'scc_initialize': scc.c:85:14: warning: assignment from incompatible pointer type [enabled by default] Fix these. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
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