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* treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-23-1/+1
| | | | | | | | | | | Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
* powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPLSumit Garg2016-07-21-0/+16
| | | | | | | | | | | | | | | | As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc/SECURE_BOOT: Add PAMU driverAneesh Bansal2016-02-24-0/+489
| | | | | | | | | | | | | | | | PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arch/powperpc: Fix start_align due to use of __ffs64() instead ffs64()Ashish kumar2016-01-25-2/+2
| | | | | | | | | | | | Incorrect DDR law was created in case of B4860qds after commit 2d2f490d. Return value of ffs64() differs from __ffs64(), eg. ffs64(0x80000000) = 0x20 __ffs64(0x80000000) = 0x1f As a result of this change, callers need to adjust the expected return value by removing -1. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Add more SPDX-License-Identifier tagsTom Rini2016-01-19-3/+1
| | | | | | | | | In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
* Various Makefiles: Add SPDX-License-Identifier tagsTom Rini2015-11-10-3/+1
| | | | | | | | | | | After consulting with some of the SPDX team, the conclusion is that Makefiles are worth adding SPDX-License-Identifier tags too, and most of ours have one. This adds tags to ones that lack them and converts a few that had full (or in one case, very partial) license blobs into the equivalent tag. Cc: Kate Stewart <kstewart@linuxfoundation.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* powerpc: Remove __ilog2_u64 and ffs4 from bitopsFabio Estevam2015-11-05-2/+3
| | | | | | | | | | | | | Remove __ilog2_u64 and ffs4 from powerpc bitops to align with the kernel implementation. Use the generic __ffs64 instead of a custom powerpc implementation. Cc: York Sun <yorksun@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
* powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCsShaveta Leekha2015-03-04-1/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code provides framework for heterogeneous multicore chips based on StarCore and Power Architecture which are chasis-2 compliant, like B4860 and B4420 It will make u-boot recognize all non-ppc cores and peripherals like SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs. Example boot logs of B4860QDS: U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45) CPU0: B4860E, Version: 2.2, (0x86880022) Core: e6500, Version: 2.0, (0x80400120) Clock Configuration: CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz, DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz, DSP CPU4:1200 MHz, DSP CPU5:1200 MHz, CCB:666.667 MHz, DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz CPRI:600 MHz MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz FMAN1: 666.667 MHz QMAN: 333.333 MHz Top level changes include: (1) Top level CONFIG to identify HETEROGENUOUS clusters (2) CONFIGS for SC3900/DSP components (3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO" updated for dsp cores and other components (3) APIs to get DSP num cores and their Mask like: cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC (5) Code to fetch and print SC cores and other heterogenous device's frequencies (6) README added for the same Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* crypto/fsl: Add fixup for crypto nodeRuchika Gupta2015-01-23-170/+0
| | | | | | | | | | | Era property is added in the crypto node in device tree. Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to drivers/sec/sec.c so that it can be used across arm and powerpc platforms having crypto node. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> [York Sun: Fix commit message indentation] Reviewed-by: York Sun <yorksun@freescale.com>
* arch/powerpc: Initialize VSC9953 L2 SwitchCodrin Ciubotariu2015-01-21-0/+5
| | | | | | | This patch initializes VSC9953 L2 Switch for boards that have CONFIG_VSC9953 defined in their config file. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
* drivers: usb: Make usb device-tree fixup code architecture independentNikhil Badola2014-12-11-104/+0
| | | | | | | | | move usb device tree fixup code from "arch/powerpc/" to "drivers/usb/" so that it works independent of architecture it is running on Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Add T1024/T1023 SoC supportShengzhou Liu2014-12-05-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl_sec : Change accessor function to take care of endiannessRuchika Gupta2014-10-16-2/+2
| | | | | | | | | | | SEC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of SEC IP. So update acessor functions with common SEC acessor functions to take care both type of endianness. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/8xxx: Fix in USB device-tree fixupramneek mehresh2014-09-24-11/+9
| | | | | | | | | | | | | | | | Fix following issues in USB device-tree fixup: - returns when either dr_mode or phy_type not defined. This was terminating fix-up when only either property was defined in hwconfig string - updates dr_mode_type or dr_phy_type with junk value when their index is -1. Now these are updated only when their respective index is pointing to relevant types in modes[] and phys[] array - dr_mode_type and dr_phy_type were not NULL for each controller Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Removed support for G4060Sandeep Singh2014-07-22-1/+0
| | | | | | | G4060 has no PA cores, hence removing its support. Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Added B4460 supportShaveta Leekha2014-05-16-0/+1
| | | | | | | | | | | B4460 differs from B4860 only in number of CPU cores, hence used existing support for B4860. B4460 has 2 PPC cores whereas B4860 has 4 PPC cores. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* PPC 85xx QEMU: Always assume 1 coreAlexander Graf2014-05-13-2/+2
| | | | | | | | | | | | | | | We only need u-boot to bother about a single core in the QEMU machine. Everything that would require additional knowledge of more cores gets handled by QEMU and passed straight into the payload we execute. Because of this setup, it would be counterproductive to enable SMP support in u-boot. We would have to rip CPUs out of already existing spin tables and respin them from u-boot. It would be a pretty big mess. So only assume we have a single core. This fixes errors about CONFIG_MP being disabled. Signed-off-by: Alexander Graf <agraf@suse.de>
* powerpc/85xx: add T4080 SoC supportShengzhou Liu2014-05-13-0/+1
| | | | | | | | The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* powerpc/mpc85xx:Disable non DDR LAWs before init_lawPrabhakar Kushwaha2014-04-22-9/+33
| | | | | | | | | Before parsing LAW table i.e. init_law, boot loader should disable all previous LAWs except DDR LAWs which has been created by previous pre boot loader during DDR initialization. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: SECURE BOOT- Disable law 0 for non PBL platformsAneesh Bansal2014-04-22-0/+10
| | | | | | | | | ISBC creates a LAW 0 entry for non PBL platforms, which is not disabled before transferring the control to uboot. The LAW 0 entry has to be disabled. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Makefile: Select objects by CONFIG_ rather than $(ARCH) or $(CPU)Masahiro Yamada2013-12-16-4/+2
| | | | | | | | | | | | | | | | | Convert like follows: CPU mpc83xx -> CONFIG_MPC83xx CPU mpc85xx -> CONFIG_MPC85xx CPU mpc86xx -> CONFIG_MPC86xx CPU mpc5xxx -> CONFIG_MPC5xxx CPU mpc8xx -> CONFIG_8xx CPU mpc8260 -> CONFIG_8260 CPU ppc4xx -> CONFIG_4xx CPU x86 -> CONFIG_X86 ARCH x86 -> CONFIG_X86 ARCH powerpc -> CONFIG_PPC Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc/mpc85xx: Add T2080/T2081 SoC supportShengzhou Liu2013-11-25-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* Driver/IFC: Move Freescale IFC driver to a common driverYork Sun2013-11-25-141/+0
| | | | | | | | Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-25-7404/+0
| | | | | | | Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc: move mpc8xxx entry under arch/powerpc/cpu/Masahiro Yamada2013-11-17-0/+6
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-46/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Note: arch/powerpc/cpu/mpc8260/Makefile is originally like follows: ---<snip>--- START = start.o kgdb.o COBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \ ---<snip>--- COBJS-$(CONFIG_ETHER_ON_SCC) = ether_scc.o ---<snip>--- $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o) The link rule `$(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o)' is weird. kbdg.o is not included in $(OBJS) but linked into $(LIB) and $(LIB) is not dependent on kgdb.o. (Broken dependency tracking) So, START = start.o kgdb.o shoud have been START = start.o SOBJS = kgdb.o That is why this commit adds kgdb.o to obj-y, not to extra-y. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de>
* mpc8xxx: set x2 DDR3 refresh rate if SPD config requires itValentin Longchamp2013-10-24-1/+16
| | | | | | | | | | | | | | | If the DDR3 module supports industrial temperature range and requires the x2 refresh rate for that temp range, the refresh period must be 3.9us instead of 7.8 us. This was successfuly tested on kmp204x board with some MT41K128M16 DDR3 RAM chips (no module used, chips directly soldered on board with an SPD EEPROM). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix minor conflicts in fsl_ddr_dimm_params.h, lc_common_dimm_params.c, common_timing_params.h] Acked-by: York Sun <yorksun@freescale.com>
* mpc8xxx: call i2c_set_bus_num in __get_spdValentin Longchamp2013-10-24-1/+5
| | | | | | This is necessary with the new I2C subystem that was introduced lately. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
* powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socsramneek mehresh2013-10-24-2/+4
| | | | | | | | CONFIG_USB_MAX_CONTROLLER_COUNT macro recently defined for initializing all USB controllers on a given platform. This macro is defined for all 85xx socs Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* powerpc: Fix CamelCase warnings in DDR related codePriyanka Jain2013-10-16-424/+424
| | | | | | | | | | | Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h has various parameters with embedded acronyms capitalized that trigger the CamelCase warning in checkpatch.pl Convert those variable names to smallcase naming convention and modify all files which are using these structures with modified structures. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* powerpc: Use print_size() where appropriateShruti Kanetkar2013-08-20-1/+2
| | | | | | | | Makes the startup output more consistent Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc: mpc85xx: Support booting from SD Card with SPLYing Zhang2013-08-20-0/+4
| | | | | | | | | | | | | | | | The code from the internal on-chip ROM. It loads the final uboot image into DDR, then jump to it to begin execution. The SPL's size is sizeable, the maximum size must not exceed the size of L2 SRAM. It initializes the DDR through SPD code, and copys final uboot image to DDR. So there are two stage uboot images: * spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that ddr spd code can get the interleaving mode setting in env. It loads final uboot image from offset 96KB. * final uboot image, size is variable depends on the functions enabled. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc: deleted unused symbol CONFIG_SPL_NAND_MINIMAL and enabled some ↵Ying Zhang2013-08-20-2/+4
| | | | | | | | | | | functionality for common SPL 1. The symbol CONFIG_SPL_NAND_MINIMAL is unused, so deleted it. 2. Some functions were unused in the minimal SPL, but it is useful in the common SPL. So, enabled some functionality for common SPL. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/usb: Depricate usb_phy_type and usb_dr_mode uboot env variablesramneek mehresh2013-08-14-22/+0
| | | | | | | | | Remove getting values of usb mode and phy_type from "usb_dr_mode" and "usb_phy_type" uboot env variables. Now, these are determined only from hwconfig string Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: Fix TIMING_CFG_3[EXT_ACTTOPRE]James Yang2013-08-09-1/+1
| | | | | | | | The TIMING_CFG_3[EXT_ACTTOPRE] register field is 2 bits wide, but the mask omitted the LSB. This patch provides a 2-bit wide mask. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/85xx: Add C29x SoC supportMingkai Hu2013-08-09-0/+3
| | | | | | | | | | | | | | | The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com>
* powerpc/mpc8xxx: Add memory reset controlYork Sun2013-08-09-8/+48
| | | | | | | | | JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: Add x4 DDR device supportYork Sun2013-08-09-0/+11
| | | | | | | | | On selected platforms, x4 DDR devices can be supported. Using x4 devices may lower the performance, but generally they are available for higher density. Tested on MT36JSF2G72PZ-1G9E1 RDIMM. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffffYork Sun2013-08-09-3/+9
| | | | | | | | | | | | When chip select interleaving is enabled, cs0_bnds is used for address binding. Other csn_bnds are not used. When two controllers interleaving is enabled, cs0_bnds of both controllers are used, other csn_bnds are not. However, the unused csn_bnds may be used internally for calculating addresses for calibration. Setting those registers to 0 may confuse controllers in some cases. Instead, setting them to 0xffffffff together with normal LAWs will guarantee the address is not mapped to DDR. Signed-off-by: York Sun <yorksun@freescale.com>
* mpc85xx: Base emulator supportYork Sun2013-08-09-0/+5
| | | | | | | | | Prepare for emulator support for mpc85xx parts. Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers. These two registers improve stability but not supported by emulator. Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base. Signed-off-by: York Sun <yorksun@freescale.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-90/+8
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* fsl_ifc: add support for different IFC bank countMingkai Hu2013-06-20-1/+57
| | | | | | | | | | | | Calculate reserved fields according to IFC bank count 1. Move csor_ext register behind csor register and fix res offset 2. Move ifc bank count to config_mpc85xx.h to support 8 bank count 3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile error on some devices that does not have IFC controller. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/boot: Change the macro of Boot from SRIO and PCIE master moduleLiu Gang2013-06-20-2/+2
| | | | | | | | | | | | | | | | | Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:No NOR boot, do not compile IFC errata A003399Prabhakar Kushwaha2013-06-20-1/+1
| | | | | | | | IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or no NOR boot, do not compile its workaround. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8xxx: Allow DDR overclockYork Sun2013-05-24-2/+0
| | | | | | | | | | Allow DDR clock runs faster than SPD specifes. This may cause memory failure, but the user should know what is going to happen when using higher than expected DDR clock. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/chassis2: Change core numbering schemeYork Sun2013-05-24-9/+44
| | | | | | | | | | | | | | | To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8xxx: Add T1040 and variant SoCsYork Sun2013-05-24-0/+6
| | | | | | | | | T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8xxx: Allow board file to override DDR address assignmentYork Sun2013-05-14-1/+6
| | | | | | | | | This gives boards flexibility to assign other than default addresses to each DDR controller. For example, DDR controler 2 can have 0 as the base and DDR controller 1 has higher memory. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Add T4160 SoCYork Sun2013-05-14-0/+1
| | | | | | | | | | T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8xxx: Fix DDR 3-way interleavingYork Sun2013-05-14-8/+11
| | | | | | | Should check if interleaving is enabled before using interleaving mode. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit v1.1 at 2024-11-08 20:03:52 +0000