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* arch/powerpc/cpu/mpc8xxx/ddr/interactive.c: Fix GCC 4.6 build warningKumar Gala2011-11-29-2/+1
| | | | | | | | | Fix: interactive.c: In function 'fsl_ddr_interactive': interactive.c:1357:15: warning: variable 'len' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8xxx: update module_type values from JEDEC DDR3 SPD SpecificationIra W. Snyder2011-11-29-0/+7
| | | | | | | | | | Newer JEDEC DDR3 SPD Specifications define several additional values for the DDR3 module_type field which were undefined when this code was written. Update the code to handle the newer module types. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c: Fix GCC 4.6 build warningKumar Gala2011-11-11-5/+2
| | | | | | | | | | | | Fix: ctrl_regs.c: In function 'set_ddr_sdram_cfg_2': ctrl_regs.c:641:15: warning: variable 'rcw_en' set but not used [-Wunused-but-set-variable] ctrl_regs.c: In function 'compute_fsl_memctl_config_regs': ctrl_regs.c:951:31: warning: array subscript is above array bounds [-Warray-bounds] ctrl_regs.c:752:34: warning: array subscript is above array bounds [-Warray-bounds] Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* arch/powerpc/cpu/mpc8xxx/ddr/options.c: Fix GCC 4.6 build warningKumar Gala2011-11-11-0/+4
| | | | | | | | | Fix: options.c: In function 'populate_memctl_options': options.c:486:28: warning: variable 'pdodt' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* GCC4.6: Squash warnings in ddr[123]_dimm_params.cMarek Vasut2011-10-27-3/+3
| | | | | | | | | | | | | | | | | | | | ddr1_dimm_params.c: In function 'compute_ranksize': ddr1_dimm_params.c:44: warning: format '%08x' expects type 'unsigned int', but argument 2 has type 'long long unsigned int' ddr2_dimm_params.c: In function 'compute_ranksize': ddr2_dimm_params.c:43: warning: format '%08x' expects type 'unsigned int', but argument 2 has type 'long long unsigned int' ddr3_dimm_params.c: In function 'compute_ranksize': ddr3_dimm_params.c:74: warning: format '%16lx' expects type 'long unsigned int', but argument 2 has type 'long long unsigned int' Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Add support for interactive DDR programming interfaceYork Sun2011-10-09-17/+1726
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Interactive DDR debugging provides a user interface to view and modify SPD, DIMM parameters, board options and DDR controller registers before DDR is initialized. With this feature, developers can fine-tune DDR for board bringup and other debugging without frequently having to reprogram the flash. To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header file and set an environment variable to activate it. Syntax: setenv ddr_interactive on After reset, U-boot prompts before initializing DDR controllers FSL DDR> The available commands are print print SPD and intermediate computed data reset reboot machine recompute reload SPD and options to default and recompute regs edit modify spd, parameter, or option compute recompute registers from current next_step to end next_step shows current next_step help this message go program the memory controller and continue with u-boot The first command should be "compute", which reads data from DIMM SPDs and board options, performs the calculation then stops before setting DDR controller. A user can use "print" and "edit" commands to view and modify anything. "Go" picks up from current step with any modification and compltes the calculation then enables the DDR controller to continue u-boot. "Recompute" does it over from fresh reading. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driverYork Sun2011-09-29-4/+9
| | | | | | | | | | | | | | | | | Unified DDR driver is maintained for better performance, robustness and bug fixes. Upgrading to use unified DDR driver for MPC83xx takes advantage of overall improvement. It requires changes for board files to customize platform-dependent parameters. To utilize the unified DDR driver, a board needs to define CONFIG_FSL_DDRx in the header file. No more boards will be accepted without such definition. Note: the workaround for erratum DDR6 for the very old MPC834x Rev 1.0/1.1 and MPC8360 Rev 1.1/1.2 parts is not migrated to unified driver. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Add DDR2 to unified DDR driverYork Sun2011-09-29-17/+230
| | | | | | | | | | | | DDR2 has different ODT table and values. Adding table according to Samsung application note. Fix additive latency calculation to avoid interger underflow. Also converted typedef dynamic_odt_t to struct dynamic_odt. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()York Sun2011-09-29-15/+11
| | | | | | | Reduce the calculation error to 1ps. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slotsYork Sun2011-09-29-4/+7
| | | | | | | The two slots on the same controller have different addresses. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_enYork Sun2011-09-29-9/+10
| | | | | | | | Check second DIMM slot in case the first one is empty. Honor DQS enable option for SDRAM mode register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Move DDR RCW overriding to common codeYork Sun2011-09-29-0/+15
| | | | | | | | DDR RCW varies at different speeds. It is common for all platform. Move it out from corenet_ds. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Extend CWL tableYork Sun2011-09-29-2/+16
| | | | | | | Extend CAS write Latency (CWL) table to comply with DDR3 spec Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Allow override DDR read-to-write turnaround timeYork Sun2011-07-11-0/+3
| | | | | | | Add this option to allow boards to override the default read-to-write turnaround time for better performance. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: fix DDR data width checkingYork Sun2011-07-11-8/+27
| | | | | | | | | Checking width before setting DDR controller. SPD for DDR1 and DDR2 has data width and primary sdram width. The latter one has different meaning for DDR3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Adding fallback to raw timing on supported boardsYork Sun2011-07-11-0/+8
| | | | | | | | In case of empty SPD or checksum error, fallback to raw timing on supported boards. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Enable calculation for fixed DDR chipsYork Sun2011-07-11-2/+30
| | | | | | | | | | We used to have fixed parameters for soldered DDR chips. This patch introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing data from DDR chip datasheet, implemneted in board-specific files or header files. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Add 16-bit support for DDR3York Sun2011-07-11-2/+15
| | | | | | | | Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit DDR devices. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: check SPD length before using part numberYork Sun2011-07-11-1/+2
| | | | | | | | Only use DDR DIMM part number if SPD has valid length, to prevent from display garbage in case SPD doesn't cover these fields. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: adjust DDR burst length and chop accroding to sdram widthYork Sun2011-07-11-4/+20
| | | | | | | | If the bus width is 32-bit, burst chop should be disabled and burst length should be 8. Read from SPD or other source to determine the width. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: reword max tCKmin messageYork Sun2011-05-13-3/+3
| | | | | | | | Reword "The DIMM max tCKmin is ..." to "The DDR clock is faster than the slowest DIMM(s) can support". Fixed interger type in printf as well. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl-ddr: Fix mixed-case macro namesKyle Moffett2011-04-29-9/+9
| | | | | Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Fix typo for address hashing messageKumar Gala2011-04-04-1/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8xxx: DDR2/DDR3: Clean up DIMM-type switch statementsKyle Moffett2011-04-04-33/+33
| | | | | | | | | | | | | | | The numeric constants in the switch statements are replaced by #defines added to the common ddr_spd.h header. This dramatically improves the readability of the switch statments. In addition, a few of the longer lines were cleaned up, and the DDR2 type for an SO-RDIMM module was added to the DDR2 switch statement. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_ddr: Don't use full 64-bit divides on 32-bit PowerPCKyle Moffett2011-04-04-16/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit integer divide operations to convert between nanoseconds and DDR clock cycles given arbitrary DDR clock frequencies. Since all of the inputs to this are 32-bit (nanoseconds, clock cycles, and DDR frequencies), we can easily restructure the computation to use the "do_div()" function to perform 64-bit/32-bit divide operations. On 64-bit this change is basically a no-op, because do_div is implemented as a literal 64-bit divide operation and the instruction scheduling works out almost the same. On 32-bit PowerPC a fully accurate 64/64 divide (__udivdi3 in libgcc) is over 1.1kB of code and thousands of heavily dependent cycles to compute, all of which is linked from libgcc. Another 1.2kB of code comes in for the function __umoddi3. It should be noted that nothing else in U-Boot or the Linux kernel seems to require a full 64-bit divide on my 32-bit PowerPC. Build-and-boot-tested on the HWW-1U-1A board using DDR2 SPD detection. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Acked-by: York Sun <yorksun@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_ddr: Adds 16 bit DDR Data width optionPoonam Aggrwal2011-04-04-1/+3
| | | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Display DIMM modelYork Sun2011-04-04-4/+7
| | | | | | | | Beside displaying RDIMM or UDIMM, this patch adds display of the model numbers embedded in SPD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from boardKumar Gala2011-04-04-3/+60
| | | | | | | | | | | | | | Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()Kumar Gala2011-04-04-6/+3
| | | | | | | | | | Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq() and every 86xx board uses get_bus_freq(). If implement get_ddr_freq() as a static inline to call get_bus_freq() we can remove fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq() directly. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: disable rcw_en bit for non-DDR3York Sun2011-03-24-0/+2
| | | | | | | | rcw_en bit is only available for DDR3 controllers. It is a reserved bit on DDR1 and DDR2 controllers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: fix recognition of DIMMs with ECC and Address ParityYork Sun2011-03-24-1/+2
| | | | | | | | To recognize DIMMs with ECC capability by testing ECC bit only. Not to be confused by Address Parity bit. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registersYork Sun2011-03-05-6/+14
| | | | | | | | | The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3York Sun2011-02-10-1/+4
| | | | | | | | | When DDR data rate is higher than 1200MT/s or controller interleaving is enabled, additional cycle for write-to-read turnaround is needed to satisfy dynamic ODT timing. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Fix compile warning when build for a DDR1 or DDR2 boardKumar Gala2011-01-24-1/+1
| | | | | | | | | ctrl_regs.c: In function 'set_ddr_sdram_mode_2': ctrl_regs.c:690:6: warning: unused variable 'i' 'i' is only used by DDR3 code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Enable unique mode registers and dynamic ODT for DDR3York Sun2011-01-19-54/+506
| | | | | | | | | | | | | | | | | | Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version (major, minor, errata) to determine if unique mode registers are available. If true, always use unique mode registers. Dynamic ODT is enabled if needed. The table is documented in doc/README.fsl-ddr. This function may also need to be extend for future other platforms if such a feature exists. Enable address parity and RCW by default for RDIMMs. Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for quad-rank RDIMMs. Use a formula to calculate rodt_on for timing_cfg_5. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8xxx: Enable ECC on/off control in hwconfigYork Sun2011-01-19-3/+6
| | | | | | | | | | | | | | Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file, ECC can be turned on/off by this switch. If this switch is omitted, it is ON by default. Updated hwconfig calls to use local buffer. Syntax is hwconfig=fsl_ddr:ecc=on Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8xxx: Display RDIMM if detectedYork Sun2011-01-19-12/+8
| | | | | | | Print a message when a RDIMM is detected. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Add hwconfig APIs to address early parsing used by DDR initKumar Gala2011-01-19-19/+59
| | | | | | | | | | | | | | | | | | | | | | | | | There are several users of the hwconfig APIs (8xxx DDR) before we have the environment properly setup. This causes issues because of the numerous ways the environment might be accessed because of the non-volatile memory it might be stored in. Additionally the access might be so early that memory isn't even properly setup for us. Towards resolving these issues we provide versions of all the hwconfig APIs that can be passed in a buffer to parse and leave it to the caller to determine how to allocate and populate the buffer. We use the _f naming convention for these new APIs even though they are perfectly useable after relocation and the environment being ready. We also now warn if the non-f APIs are called before the environment is ready to allow users to address the issues. Finally, we convert the 8xxx DDR code to utilize the new APIs to hopefully address the issue once and for all. We have the 8xxx DDR code create a buffer on the stack and populate it via getenv_f(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* 8xxx/ddr: add support to only compute the ddr sdram sizeHaiying Wang2011-01-19-9/+40
| | | | | | | | | This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in case that the DDR SDRAM is initialized in the 2nd stage uboot and should not be intialized again in the final stage uboot. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Move fsl_is_spd() into generic 8xxx ddr codeKumar Gala2011-01-14-1/+21
| | | | | | | | Move the parsing of hwconfig to determine if to use spd into common code so we can share it across all boards instead of duplicating it everywhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC8xxx DDR: align informational printsBecky Bruce2011-01-14-2/+3
| | | | | | | | | | | | | | | | | | | | Add spaces to cause the informational prints to line up with the ones from init_func_ram() in board.c. Output now looks like this: .... DRAM: Detected 4096 MB of memory This U-Boot only supports < 4G of DDR You could rebuild it with CONFIG_PHYS_64BIT DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC off) .... The prints from lbc_sdram_init() have also been modified to line line up and changed to start with "LBC SDRAM" instead of the confusing "SDRAM". Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Switch from archive libraries to partial linkingSebastien Carlier2010-11-17-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, weak symbols were not overridden by non-weak symbols found in archive libraries when linking with recent versions of binutils. As stated in the System V ABI, "the link editor does not extract archive members to resolve undefined weak symbols". This commit changes all Makefiles to use partial linking (ld -r) instead of creating library archives, which forces all symbols to participate in linking, allowing non-weak symbols to override weak symbols as intended. This approach is also used by Linux, from which the gmake function cmd_link_o_target (defined in config.mk and used in all Makefiles) is inspired. The name of each former library archive is preserved except for extensions which change from ".a" to ".o". This commit updates references accordingly where needed, in particular in some linker scripts. This commit reveals board configurations that exclude some features but include source files that depend these disabled features in the build, resulting in undefined symbols. Known such cases include: - disabling CMD_NET but not CMD_NFS; - enabling CONFIG_OF_LIBFDT but not CONFIG_QE. Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
* Disable unused chip-select for DDR controller interleavingYork Sun2010-10-20-3/+14
| | | | | | | | When DDR controller interleaving is eabled and less than all bank (chip-select) interleaving is seletected, the unused chip-select should be disabled. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fix parameters to support RDIMM for P2020DSYork Sun2010-08-31-0/+1
| | | | | Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Improvement to DDR parametersyork2010-07-26-7/+8
| | | | | | Changes for P2020DS DDR applies to other 8xxx platform Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/8xxx: Enable DDR3 RDIMM supportyork2010-07-26-53/+55
| | | | | | | | | Enabled registered DIMMs using data from SPD. RDIMMs have registers which need to be configured before using. The register configuration words are stored in SPD byte 60~116 (JEDEC standard No.21-C). Software should read those RCWs and put into DDR controller before initialization. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/8xxx: Enabled address hashing for 85xxyork2010-07-26-0/+17
| | | | | | | For 85xx silicon which supports address hashing, it can be activated by hwconfig. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/8xxx: Enable quad-rank DIMMs.york2010-07-26-21/+60
| | | | | | | Previous code presumes each DIMM has up to two rank (chip select). Newer DDR controller supports up to four chip select on one DIMM. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4york2010-07-26-77/+184
| | | | | | | | | Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual rank with 512MB each rank. Also check dimm size and rank size for memory controller interleaving Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/8xxx: Enabled hwconfig for memory interleavingKumar Gala2010-07-26-15/+25
| | | | | | | | | | | | | | | | | | | | | Replace environmental variables memctl_intlv_ctl and ba_intlv_ctl with hwconfig parameters. The syntax is setenv hwconfig "fsl_ddr:ctlr_intlv=<mode>,bank_intlv=<mode>" The mode values for memory controller interleaving are cacheline page bank superbank The mode values for bank interleaving are cs0_cs1 cs2_cs3 cs0_cs1_and_cs2_cs3 cs0_cs1_cs2_cs3 Signed-off-by: York Sun <yorksun@freescale.com>
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