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* arch/powerpc: Add SGMII support for the L2 Switch portsCodrin Ciubotariu2015-01-16-4/+10
| | | | | | | | | Some Freescale SoCs like T1020 and T1040 have an integrated L2 Switch. The L2 Switch ports may be connected to Ethernet PHYs over SGMII and QSGMII. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arch/powerpc: Fix mapping of Freescale SerDes protocolsCodrin Ciubotariu2015-01-16-30/+37
| | | | | | | | | | | | | | | | The number of supported serdes protocols on Freescale SoCs has increased over time. Until now, an u64 variable have been initialized on boot with the configured protocols. However, since this number has increased (enum srds_prtcl has more than 64 values), 64 bits are no longer sufficient to hold track of all the configured protocols. This patch replaces the u64 map values with static arrays. To keep track of the number of serdes protocols, the SERDES_PRCTL_COUNT vale has been added at the end of enum srds_prtcl. This value must always be the last one. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx: clean up the old deep sleep frameworktang yuantian2015-01-16-9/+1
| | | | | | | | | All the boards that support deep sleep feature are converted to deep sleep generic board interface. The old interface which support non-generic board is not used anymore. So clean it up. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t1024: add serdes protocol 0x40 and 0x5fShengzhou Liu2015-01-16-0/+2
| | | | | | | Add serdes protocol 0x40 and 0x5f. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* b4860: Correct LIODN assignment for PCIeTudor Laurentiu2015-01-16-1/+1
| | | | | | | | | | | For B4 the LIODN register for PCIe is in PCIe address space and not in GUTs Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* p5040ds: changed liodn offsetsTudor Laurentiu2014-12-15-12/+12
| | | | | | | | | Offsets were overlaping, causing pamu access violations in hypervised scenarios. Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx: inhibit qman and bman portals by defaultJeffrey Ladouceur2014-12-15-0/+43
| | | | | | | | | Not all portals might be managed and therefore visible. Set the isdr register so that the corresponding isr register won't be set. This is required when supporting power management. Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Fix DDR TLB mapping leftoverYork Sun2014-12-15-4/+8
| | | | | | | | | | Commit f29f804a93e87c17670607641d120f431a3b0633 generalized the TLB mapping function, but made the DDR mapping leftover size to zero, causing the message not printed. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alexander Graf <agraf@suse.de> CC: Scott Wood <scottwood@freescale.com>
* powerpc/mpc85xx: use correct dma compatible for several SoCsTudor Laurentiu2014-12-05-21/+21
| | | | | | | | | | | | | | Newer qoriq socs have an updated dma ip block with a different compatible. Let's make sure we use the proper string so that the dmas get their liodn. In order to have the means to specify the compatible string, the liodn setting macros were updated to receive a new parameter for it. The following SoCs were changed to use the new compatible: T1023/4, T1040, T2080/1, T4240, B4860. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t1024rdb: Add T1024 RDB board supportShengzhou Liu2014-12-05-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC. T1024RDB board Overview ----------------------- - T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3L SDRAM memory controller with ECC and interleaving support - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - one 10Gbps XFI interface - PCIe: Three PCIe controllers: one PCIe Slot and two Mini-PCIe connectors. - SerDes: 4 lanes up to 10.3125GHz - IFC: 128MB NOR Flash, 512MB NAND Flash and CPLD - eSPI: 64MB N25Q512 SPI flash. - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - USB: Two Type-A USB2.0 ports with internal PHY - eSDHC: Support SD, SDHC, SDXC and MMC/eMMC - I2C: Four I2C controllers - UART: Two UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT Fix Kconfig by adding SUPPORT_SPL] Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t1024qds: Add T1024 QDS board supportShengzhou Liu2014-12-05-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1024QDS is a high-performance computing evaluation, development and test platform for T1024 QorIQ Power Architecture processor. T1024QDS board Overview ----------------------- - T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - Three 1G/2.5Gbps SGMII ports - Four 1Gbps QSGMII ports - one 10Gbps XFI or 10Base-KR interface - SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and Aurora - PCIe: Three PCI Express controllers with five PCIe slots. - IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA - Video: DIU supports video up to 1280x1024x32 bpp. - Chrontel CH7201 for HDMI connection. - TI DS90C387R for direct LCD connection. - Raw (not encoded) video connector for testing or other encoders. - QUICC Engine block - 32-bit RISC controller for flexible support of the communications peripherals - Serial DMA channel for receive and transmit on all serial channels - Two universal communication controllers, supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - eSPI: Three SPI flash devices. - SATA: one SATA 2.O. - USB: Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB) - eSDHC: Support SD, SDHC, SDXC and MMC/eMMC. - I2C: Four I2C controllers. - UART: Two UART on board. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: Fix ft_board_setup() type, fix MAINTAINERS for SECURE_BOOT Fix Kconfig by adding SUPPORT_SPL] Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Add T1024/T1023 SoC supportShengzhou Liu2014-12-05-1/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Update LIODN entries for T1040Priyanka Jain2014-12-05-7/+19
| | | | | Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/b4860qds: add workaround for XFIShaohui Xie2014-12-05-0/+4
| | | | | | | | | | | | | | | XFI does not work stable on current board, it's due to heat sink issue, to make it work stable the board needs additional heat sink, enable two XFI lanes only. Right now we do not have such an erratum for the issue, so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it. The workaround will only be used in XFI protocols and only if the hwconfig indicates that XFI is prefered. A new VSC3308 config function is used instead of re-use the original function, to avoid making the function complex and ugly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* 85xx/b4860: Add alternate serdes protocols for B4860/B4420Shaveta Leekha2014-12-05-0/+19
| | | | | | | | | | | | | | | | Addded Alternate options with LC VCO for following protocols: 0x02 --> 0x01 0x08 --> 0x07 0x18 --> 0x17 0x1E --> 0x1D 0x49 --> 0x48 0x6F --> 0x6E 0x9A --> 0x99 0x9E --> 0x9D Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: modify erratum A007186Zhao Qiang2014-12-05-2/+4
| | | | | | | | | | | T2080 v1.0 has this errata while v1.1 has fixed this errata by hardware, add a new function has_errata_a007186 to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first, if the sil has errata a007186, then run the errata code, if not, doesn't run the code. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/t104xrdb: Conditional workaround of errata A-008044Prabhakar Kushwaha2014-12-05-1/+2
| | | | | | | | | | Workaround of Errata A-008044 was implemented without errata number and it is enabled by default. Errata A-008044 is only valid for T1040 Rev 1.0. So put errata number and make it conditional. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx:Put errata number for T104x NAND boot issuePrabhakar Kushwaha2014-12-05-1/+4
| | | | | | | | | | | | When device is configured to load RCW from NAND flash IFC_A[16:31] are driven low after RCW loading. Hence Devices connected on IFC_CS[1:7] and using IFC_A[16:31] lines are not accessible. Workaround is already in-place. Put the errata number to adhere errata handling framework. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx/t2080: Fix parsing DDR ratio for new revisionYork Sun2014-12-05-3/+20
| | | | | | | | T2080 rev 1.1 changes MEM_RAT in RCW, which requires new parsing for ratio, the same way as T4240 rev 2.0. Signed-off-by: York Sun <yorksun@freescale.com> CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* powerpc/t2080: add serdes2 protocol 0x2eShengzhou Liu2014-12-05-0/+1
| | | | | | | Add serdes2 protocol 0x2e. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-11-26-0/+5
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| * drivers : usb: fsl: Implement usb Erratum A007798 workaroundNikhil Badola2014-11-24-0/+4
| | | | | | | | | | | | | | | | Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large usb writes Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers: usb: fsl: Move USB Errata checking codeNikhil Badola2014-11-21-0/+1
| | | | | | | | | | | | | | | | | | | | Move USB Errata checking code from "arch/powerpc" to architecture independent file "fsl_usb.h" so that errata(s) become independent of the architecture. For each erratum checking function for PPC arch, define a nop function for non PPC arch for successful compilation in either case Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada2014-11-23-1/+1
|/ | | | | | | | | | | | | | | | | | | | U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
* powerpc/mpc85xx: Use IFC accessor functionPrabhakar Kushwaha2014-11-14-4/+4
| | | | | | | | | | IFC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of IFC IP. So use IFC acessor functions instead of in_be32(). Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* 85xx/b4:Correct USB DR controller liodn entryramneek mehresh2014-11-14-1/+1
| | | | | | | | | | | | | LIODN entry for B4860/B4420 mentions USB controller as "mph" insread of "dr". This results in PAMU not permitting bus transactions for USB DR controller on B4860 resulting in USB function failure. Replacing "fsl-usb2-mph" with "fsl-usb2-dr" allows USB DR controller bus transactions Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: Sethi Varun-B16395 <Varun.Sethi@freescale.com> Reviewed-by: Sun Yusong-R58495 <yorksun@freescale.com>
* cppcheck cleanup: fix nullPointer errorsWolfgang Denk2014-11-07-1/+4
| | | | | | | | | | | There are a number of places where U-Boot intentionally and legally accesses physical address 0x0000, for example when installing exception vectors on systems where these are located in low memory. Add "cppcheck-suppress nullPointer" comments to silence cppcheck where this is intentional and legal. Signed-off-by: Wolfgang Denk <wd@denx.de>
* kconfig: add CONFIG_SUPPORT_TPLMasahiro Yamada2014-10-27-0/+5
| | | | | | | | CONFIG_TPL should not be enabled for boards that do not have TPL. CONFIG_SUPPORT_TPL introduced by this commit should be "select"ed by boards with TPL support and CONFIG_TPL should depend on it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* kconfig: add CONFIG_SUPPORT_SPLMasahiro Yamada2014-10-27-0/+12
| | | | | | | | | CONFIG_SPL should not be enabled for boards that do not have SPL. CONFIG_SUPPORT_SPL introduced by this commit should be "select"ed by boards with SPL support and CONFIG_SPL should depend on it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* ppc: Zap HWW1U1A boardMarek Vasut2014-10-27-4/+0
| | | | | | | | | | | This is the only used of CONFIG_SPI_X macro, just zap this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de>
* powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure bootRuchika Gupta2014-10-16-1/+8
| | | | | | | | | | | By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl_sec: Add hardware accelerated SHA256 and SHA1Ruchika Gupta2014-10-16-0/+7
| | | | | | | | | | SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl_sec : Change accessor function to take care of endiannessRuchika Gupta2014-10-16-4/+4
| | | | | | | | | | | SEC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of SEC IP. So update acessor functions with common SEC acessor functions to take care both type of endianness. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-09-26-2/+2
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| * driver/ddr: Restruct driver to allow standalone memory spaceYork Sun2014-09-25-2/+2
| | | | | | | | | | | | | | | | | | | | U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: York Sun <yorksun@freescale.com>
* | powerpc/mpc85xx: Serdes protocol "00" is supportedEbony Zhu2014-09-24-5/+0
|/ | | | | | | | "0x00" is a valid serdes protocol for QorIQ parts, and can not be used to test whether the serdes is enabled or disabled. Signed-off-by: Ebony Zhu <b45385@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* kconfig: remove redundant "string" type in arch and board KconfigsMasahiro Yamada2014-09-13-1/+0
| | | | | | | | | | | | | | | | | | Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME} are specified in arch/Kconfig. We can delete the ones in arch and board Kconfig files. This commit can be easily reproduced by the following command: find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e ' /config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ { N s/\n[[:space:]]*string// } ' Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc/mpc85xx: Enabling CPC conditionally based on hwconfig optionsShaveta Leekha2014-08-20-2/+26
| | | | | | | | | | | If hwconfig does not contains "en_cpc" then by default all cpcs are enabled If this config is defined then only those individual cpcs which are defined in the subargument of "en_cpc" will be enabled e.g en_cpc:cpc1,cpc2; (this will enable cpc1 and cpc2) or en_cpc:cpc2; (this enables just cpc2) Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t104xrdb: support deep sleep in SPI/SD bootTang Yuantian2014-08-12-0/+15
| | | | | | | | | | | | Add deep sleep support in SPI/SD boot. The destination address second stage uboot image is loaded to is changed because currently this address will be used by kernel which means we can't reserve it for resume. Entry point to kernel is still placed in second stage uboot. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-08-06-1/+9
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| * mpc85xx: watchdog initialisation addedBoschung, Rainer2014-08-01-0/+8
| | | | | | | | | | | | | | | | Function to inititialize the cpu watchdog added. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> [York Sun: Add prototype in watchdog.h] Reviewed-by: York Sun <yorksun@freescale.com>
| * mpc85xx: fix interrupt init to not affect watchdogBoschung, Rainer2014-08-01-1/+1
| | | | | | | | | | | | | | | | TCR watchdog bit are overwritten when dec interrupt is enabled. This has been fixed with this patch. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | powerpc: remove redundant CPU definitionMasahiro Yamada2014-07-30-1/+1
| | | | | | | | | | | | | | | | CONFIG_${CPU} is defined by Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Roese <sr@denx.de>
* | kconfig: add board Kconfig and defconfig filesMasahiro Yamada2014-07-30-0/+190
|/ | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds: - arch/${ARCH}/Kconfig provide a menu to select target boards - board/${VENDOR}/${BOARD}/Kconfig or board/${BOARD}/Kconfig set CONFIG macros to the appropriate values for each board - configs/${TARGET_BOARD}_defconfig default setting of each board (This commit was automatically generated by a conversion script based on boards.cfg) In Linux Kernel, defconfig files are located under arch/${ARCH}/configs/ directory. It works in Linux Kernel since ARCH is always given from the command line for cross compile. But in U-Boot, ARCH is not given from the command line. Which means we cannot know ARCH until the board configuration is done. That is why all the "*_defconfig" files should be gathered into a single directory ./configs/. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org>
* mpc85xx/t104x: Enable L2 and CPC cache when resumeTang Yuantian2014-07-22-76/+87
| | | | | | | | | | | When resume from deep sleep, uboot needs to enable L2 and CPC cache, or they would be keeping unusable in kernel because kernel didn't enble or initialized them. This patch didn't change the existing L2 cache enabling code, just put them in a function. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/chassis2: Configure and enable L2 cache for PPC clusters onlyShaveta Leekha2014-07-22-1/+2
| | | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/85xx: add fdt_fixup_dma3Shengzhou Liu2014-07-22-0/+47
| | | | | | | | On some SoC(e.g. T2080/T4240) the 3rd DMA is not functional if SRIO2 is chosen. we add fdt_fixup_dma3() to disable the 3rd DMA if SRIO2 is chosen. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Add workaround to enable TDM on T1040Sandeep Singh2014-06-05-0/+56
| | | | | | | | | | | | | | | This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/serdes: Add the workaround for erratum A-007186Shaveta Leekha2014-06-05-0/+151
| | | | | | | | | | | | | | | | | | SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Add workaround for DDR erratum A004508York Sun2014-06-05-0/+3
| | | | | | | | | | | When the DDR controller is initialized below a junction temperature of 0°C and then operated above a junction temperature of 65°C, the DDR controller may cause receive data errors, resulting ECC errors and/or corrupted data. This erratum applies to the following SoCs and their variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023, P2020. Signed-off-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-05 10:34:27 +0000