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* net: mii: Use spatch to update miiphy_registerJoe Hershberger2016-08-15-2/+11
| | | | | | | Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* treewide: move CONFIG_PHYS_64BIT to KconfigMasahiro Yamada2016-08-05-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | We need to ensure that CONFIG_PHYS_64BIT is configured via Kconfig so that it is always available to the build system. Otherwise we can run into cases where we have inconsistent sizes of certain attributes. Ravi Babu reported offset mismatch of struct dwc3 across files since commit 95ebc253e6d4 ("types.h: move and redefine resource_size_t"). Since the commit, resource_addr_t points to phys_addr_t, whose size is dependent on CONFIG_PHYS_64BIT for ARM architecture. I tried my best to use "select" where possible (for example, ARMv8 architecture) because I think this kind of option is generally user- unconfigurable. However, I see some of PowerPC boards have 36BIT defconfigs as well as 32BIT ones. I moved CONFIG_PHYS_64BIT to the defconfigs for such boards. CONFIG_36BIT is no longer referenced, so all of the defines were removed from CONFIG_SYS_EXTRA_OPTIONS. Fixes: 95ebc253e6d4 ("types.h: move and redefine resource_size_t") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Ravi Babu <ravibabu@ti.com> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc/mpc85xx: T104x: Add nand secure boot targetSumit Garg2016-07-21-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-1/+1
| | | | | | | | | | | | | | | | | | | Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* powerpc: mpc85xx: Do not build errata command in SPLMarek Vasut2016-07-05-0/+2
| | | | | | | | | The errata command is useless in SPL, so don't build it. This fixes multiple build failures on PowerPC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: York Sun <york.sun@nxp.com> Fixes: 92623672f9d3 ("fsl: usb: make errata function common for PPC and ARM")
* arch/powerpc: Simplify some calculations using ARRAY_SIZE() macro.Robert P. J. Day2016-06-03-1/+1
| | | | | | | | Replace a number of array length calculations with the ARRAY_SIZE() macro, for clarity. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2016-05-25-0/+23
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| * powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cacheAneesh Bansal2016-05-24-0/+23
| | | | | | | | | | | | | | | | | | | | While enabling L2 cache, the value of L2PE (L2 cache parity/ECC error checking enable) must not be changed while the L2 cache is enabled. So, L2PE must be set before enabling L2 cache. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | crypto/fsl: add support for multiple SEC engines initializationAlex Porosanu2016-05-18-0/+9
|/ | | | | | | | | For SoCs that contain multiple SEC engines, each of them needs to be initialized (by means of initializing among others the random number generator). Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc: mpc85xx: Enable pre-relocation malloc for MPC85xxmario.six@gdsys.cc2016-04-08-7/+32
| | | | | | | | | | | | | To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch. We also make sure that the IVORs are always 4-aligned on e500 to prevent alignment exceptions caused by code changes in start.S. Signed-off-by: Mario Six <mario.six@gdsys.cc> Cc: York Sun <york.sun@nxp.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* fm: fdt: Move fman ucode fixup to driver codeQianyu Gong2016-02-24-120/+5
| | | | | | | | | Not only powerpc/mpc85xx but also Freescale Layerscape platforms will use fdt_fixup_fman_firmware() to insert Fman ucode blob into the device tree. So move the function to Fman driver code. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* qe: move drivers/qe/qe.h to include/fsl_qe.hQianyu Gong2016-02-24-2/+2
| | | | | | | | As the QE firmware struct is shared with Fman, move the header file out of drivers/qe/. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc/SECURE_BOOT: Add PAMU driverAneesh Bansal2016-02-24-8/+10
| | | | | | | | | | | | | | | | PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Use correct spelling of "U-Boot"Bin Meng2016-02-06-1/+1
| | | | | | | | | | Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-01-27-0/+17
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| * secure_boot: enable chain of trust for PowerPC platformsAneesh Bansal2016-01-27-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chain of Trust is enabled for PowerPC platforms for Secure Boot. CONFIG_BOARD_LATE_INIT is defined. In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add workaround for A009663Shengzhou Liu2016-01-25-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | powerpc: mpc85xx: Move set_liodns, setup_portals to common boot seqPrabhakar Kushwaha2016-01-25-0/+11
|/ | | | | | | | | | | | Users migrating Freescale's PowerPC SoC U-Boot code to their custom board, often overlook the need to execute set_liodns() and setup_portals() being called by platform files. So Move set_liodns() and setup_portals() to common u-boot boot sequence Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* fsl_*_serdes.c: Modify memset call in serdes_initTom Rini2015-12-13-1/+1
| | | | | | | | | | | GCC 5.x does not like sizeof(array_variable) and errors out. Change these calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) * SERDES_PRCTL_COUNT (the number of array elements). Cc: York Sun <yorksun@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl/errata: move fsl_errata.h to common directoryShengzhou Liu2015-12-13-3/+3
| | | | | | | | | move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix soc.h path in fsl_errata.h] Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx/u-boot*.lds: remove _GLOBAL_OFFSET_TABLE_ definitionZhenhua Luo2015-11-09-4/+0
| | | | | | | | | | | | | | | | | | | | | In binutils-2.25, the _GLOBAL_OFFSET_TABLE_ symbols defined by PROVIDE in u-boot.lds overrides the linker built-in symbols (https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commitdiff; h=b893397a4b1316610f49819344817715e4305de9), so the linker is treating _GLOBAL_OFFSET_TABLE_ as a definition into the .reloc section. To align with the change of binutils-2.25, the _GLOBAL_OFFSET_TABLE_ symbol should not be defined in sections, and the symbols in linker generated .got section should be used(https://sourceware.org/ml/binutils/2008-09/ msg00122.html) Fixed the following build errors with binutils-2.25: | powerpc-poky-linux-gnuspe-ld.bfd: _GLOBAL_OFFSET_TABLE_ not defined in linker created .got Signed-off-by: Zhenhua Luo <zhenhua.luo@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* powerpc: Remove __ilog2_u64 and ffs4 from bitopsFabio Estevam2015-11-05-0/+2
| | | | | | | | | | | | | Remove __ilog2_u64 and ffs4 from powerpc bitops to align with the kernel implementation. Use the generic __ffs64 instead of a custom powerpc implementation. Cc: York Sun <yorksun@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
* mpc85xx: Add support for the Varisys Cyrus boardAndy Fleming2015-11-04-0/+4
| | | | | | | | | | | This board runs a P5020 or P5040 chip, and utilizes an EEPROM with similar formatting to the Freescale P5020DS. Large amounts of this code were developed by Adrian Cox <adrian at humboldt dot co dot uk> Signed-off-by: Andy Fleming <afleming@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx/t2081: enable parsing DDR ratio for T2081 rev1.1Shengzhou Liu2015-11-02-1/+2
| | | | | | | | T2081 rev 1.1 changes MEM_PLL_RAT in RCW which requires new parsing for PLL ratio. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* t1040d4rdb: assign muxed pins to qe-tdm when set hwconfig qe-tdmZhao Qiang2015-11-02-0/+11
| | | | | | | | | qe-tdm is muxed with diu, if hwconfig setted as qe-tdm, assign muxed pins to qe-tdm, then delete diu node from device tree. Signed-off-by: Zhao Qiang <qiang.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc: mpc85xx: remove stxgp3, stxssa supportMasahiro Yamada2015-09-02-8/+0
| | | | | | | | These have not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Dan Malek <dan@embeddedalley.com>
* net/fman: Support both new and legacy FMan CompatiblesIgal Liberman2015-09-01-18/+72
| | | | | | | | | | | | | | Recently the FMan Port and MAC compatibles were changed. This patch aligns the FMan Port and MAC compatibles to the new FMan device tree binding document. The FMan device tree binding document can be found in the Linux kernel: ./Documentation/devicetree/bindings/powerpc/fsl/fman.txt This patch doesn't affect legacy compatibles support. Signed-off-by: Igal Liberman <igal.liberman@freescale.com> Tested-by: Xing Lei <xing.lei@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ramYork Sun2015-09-01-1/+9
| | | | | | | | | MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write through cache on E6500. L2 cache is enabled to to hold the data. This patch locks/unlocks L2 cache to ensure no data cast out from L2 cache. Signed-off-by: York Sun <yorksun@freescale.com> Reported-by: Jeffery Zhu <Jefferry.Zhu@freescale.com>
* powerpc/t4240: update serdes tableShaohui Xie2015-07-31-55/+48
| | | | | | | | | | Serdes Lanes availability on T4160 and T4080 are same, which serdes 2 & 3 support 8 Lanes, but serdes 1 & 4 support only 4 Lanes E/F/G/H, Lanes A/B/C/D are not available, updated the serdes table accordingly with some minor fix. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041Aneesh Bansal2015-07-31-0/+11
| | | | | | | | | | | | | | | | | | | Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t1024: update fman liodn for mac1Shengzhou Liu2015-07-28-2/+1
| | | | | | | | | | | | MAC1 acts as 1G/10G dual-role MAC on T1024. We introduce macro SET_FMAN_RX_10G_TYPE2_LIODN for 10G MACs which have same Port ID and same offset of address with 1G MAC. Update it to match with the setting of fman in t1024 device tree, otherwise there is no 'fsl,liodn' in /proc/device-tree/soc@ffe000000/fman@400000/port@88000/ Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arch: Make board selection choices optionalJoe Hershberger2015-05-12-0/+1
| | | | | | | | | | | | By making the board selections optional, every defconfig will include the board selection when running savedefconfig so if a new board is added to the top of the list of choices the former top's defconfig will still be correct. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Rini <trini@konsulko.com>
* powerpc/mpc85xx: Add board support for ucp1020Oleksandr G Zhadan2015-05-04-0/+4
| | | | | | | | | | New QorIQ p1020 based board support from Arcturus Networks Inc. http://www.arcturusnetworks.com/products/ucp1020/ Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com> Signed-off-by: Oleksandr G Zhadan <oleks@arcturusnetworks.com> [York Sun: remove patman tags from commit message] Reviewed-by: York Sun <yorksun@freescale.com>
* mmc: fsl_esdhc: Add peripheral clock supportYangbo Lu2015-05-04-1/+48
| | | | | | | | | | | | The SD clock could be generated by platform clock or peripheral clock for some platforms. This patch adds peripheral clock support for T1024/T1040/T2080. To enable it, define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Don't deref NULL if qman portal lacks cell-indexScott Wood2015-05-04-2/+7
| | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Madalin-Cristian Bucur <madalin.bucur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc: add 2 common dcache assembly functionsValentin Longchamp2015-05-04-20/+0
| | | | | | | | | | | | | | This patch defines the 2 flush_dcache_range and invalidate_dcache_range functions for all the powerpc architecture. Their implementation is borrowed from the kernel's misc_32.S file and replace the ones from mpc86xx and ppc4xx since they were equivalent. This is a fix for the problem introduced by this patch: http://patchwork.ozlabs.org/patch/448849/ Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t4rdb: Add SD boot support for T4240RDB boardChunhe Lan2015-05-04-0/+1
| | | | | | | | | | | | This patch adds SD boot support for T4240RDB board. SPL framework is used. PBL initializes the internal RAM and copies SPL to it. Then SPL initializes DDR using SPD and copies u-boot from SD card to DDR, finally SPL transfers control to u-boot. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> [York Sun: Fix T4240RDB_SDCARD_defcofig] Reviewed-by: York Sun <yorksun@freescale.com>
* drivers: usb: fsl: Workaround for Erratum A004477Nikhil Badola2015-05-04-0/+4
| | | | | | | | | | Add a delay of 1 microsecond before issuing soft reset to the controller to let ongoing ULPI transaction complete. This prevents corruption of ULPI Function Control Register which eventually prevents phy clock from entering to low power mode Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx/T4240EMU: Remove T4240EMU boardYork Sun2015-05-04-3/+0
| | | | | | | T4240 SoC has been available for a long time. Emulator support is no longer needed. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Use GOT when loading IVORs post-relocationScott Wood2015-05-04-15/+20
| | | | | | | | | | | | | | | | | | | | | Commit 96d2bb952bb ("powerpc/mpc85xx: Don't relocate exception vectors") simplified IVOR initialization a bit too much, failing to use the post-relocation offset. This doesn't cause a problem with normal NOR boot, in which both the pre-relocation and post-relocation addresses are 64 KiB aligned. However, if TEXT_BASE is only 4 KiB aligned, such as for NAND/SD/etc. boot on some targets, as well as the QEMU target, the post-relocation address will not be the same in the lower 16 bits, as reserve_uboot() ensures that the relocation address is always 64 KiB aligned even if the pre-relocation address was not. Use the GOT to get the proper post-relocation offsets. Fixes: 96d2bb952bb ("powerpc/mpc85xx: Don't relocate exception vectors") Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Alexander Graf <agraf@suse.de> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Tested-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/ifc: Add 64KB page supportJaiprakash Singh2015-04-23-6/+6
| | | | | | | | | | | | | | | | IFC has two register pages.Till IFC version 1.4 each register page is 4KB each.But IFC ver 2.0 register page size is 64KB each.IFC regiters structure is break into two viz FCM and RUNTIME.FCM(Flash control machine) registers are defined in PAGE0 and controls IFC generic functionality. RUNTIME registers are defined in PAGE1 and controls NAND and GPCM funcinality. FCM and RUNTIME structures defination is common for IFC version 1.4 and 2.0. Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Remove some dead codeScott Wood2015-04-20-137/+1
| | | | | | | | | | | | | | | | | | | U-Boot does not have system calls (the services it exposes to standalone commands use a different mechanism), so the syscall handler is dead code. It's also broken code, as it assumes it is located at 0xc00 -- while even before the patch to stop relocating exception vectors to 0, U-Boot had the syscall at 0x900. The critical and machine check return paths are never called -- the regular exception return path is used instead, which works because xSRR0/1 have already been saved and can be restored via the regular SRR0/1 (we don't care too much in U-Boot about taking a critical/mcheck inside another exception prolog/epilog). Also remove a few other small unused functions. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Don't relocate exception vectorsScott Wood2015-04-20-121/+57
| | | | | | | | | | | | | | | | Booke does not require exception vectors to be located at address zero. U-Boot was doing so anyway, simply because that's how it had been done on other PPC. The downside of this is that once the OS is loaded to address zero, the exception vectors have been overwritten -- which makes it difficult to diagnose a crash that happens after that point. The IVOR setup and trap entry code is simplified somewhat as a result. Also, there is no longer a need to align individual exceptions on 0x100 byte boundaries. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net: cosmetic: Fix var naming net <-> eth driversJoe Hershberger2015-04-18-2/+2
| | | | | | | | | | | | | | | Update the naming convention used in the network stack functions and variables that Ethernet drivers use to interact with it. This cleans up the temporary hacks that were added to this interface along with the DM support. This patch has a few remaining checkpatch.pl failures that would be out of the scope of this patch to fix (drivers that are in gross violation of checkpatch.pl). Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* net: Provide a function to get the current MAC addressJoe Hershberger2015-04-18-1/+1
| | | | | | | | | The current implementation exposes the eth_device struct to code that needs to access the MAC address. Add a wrapper function for this to abstract away the pointer for this operation. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* remove unnecessary version.h includesRob Herring2015-03-24-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
* powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCsShaveta Leekha2015-03-04-0/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code provides framework for heterogeneous multicore chips based on StarCore and Power Architecture which are chasis-2 compliant, like B4860 and B4420 It will make u-boot recognize all non-ppc cores and peripherals like SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs. Example boot logs of B4860QDS: U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45) CPU0: B4860E, Version: 2.2, (0x86880022) Core: e6500, Version: 2.0, (0x80400120) Clock Configuration: CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz, DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz, DSP CPU4:1200 MHz, DSP CPU5:1200 MHz, CCB:666.667 MHz, DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz CPRI:600 MHz MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz FMAN1: 666.667 MHz QMAN: 333.333 MHz Top level changes include: (1) Top level CONFIG to identify HETEROGENUOUS clusters (2) CONFIGS for SC3900/DSP components (3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO" updated for dsp cores and other components (3) APIs to get DSP num cores and their Mask like: cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC (5) Code to fetch and print SC cores and other heterogenous device's frequencies (6) README added for the same Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc: mpc85xx: remove P2020DS board supportMasahiro Yamada2015-01-23-4/+0
| | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc: mpc85xx: remove P2020COME board supportMasahiro Yamada2015-01-23-4/+0
| | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Ira W. Snyder <iws@ovro.caltech.edu>
* powerpc: mpc85xx: remove P1_P2_RDB boardsMasahiro Yamada2015-01-23-6/+0
| | | | | | | | These boards are still non-generic boards: P1011RDB, P1022RDB, P2010RDB, P2020RDB Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
generated by cgit v1.1 at 2024-07-20 05:44:15 +0000