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* powerpc: mpc85xx: Use symbolic names for cache control bitsMark Marshall2017-01-31-4/+4
| | | | | | | | We should use the symbolic names for the cache control bits. Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at> Reviewed-by: Thomas Graziadei <thomas.graziadei@omicronenergy.com> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc: QEMU_E500: Remove macro CONFIG_QEMU_E500York Sun2016-11-23-1/+1
| | | | | | | Replace CONFIG_QEMU_E500 with ARCH_QEMU_E500 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc: MPC8569: Remove macro CONFIG_MPC8569York Sun2016-11-23-2/+2
| | | | | | | Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
* powerpc/mpc85xx: T104x: Add nand secure boot targetSumit Garg2016-07-21-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cacheAneesh Bansal2016-05-24-0/+23
| | | | | | | | | | While enabling L2 cache, the value of L2PE (L2 cache parity/ECC error checking enable) must not be changed while the L2 cache is enabled. So, L2PE must be set before enabling L2 cache. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc: mpc85xx: Enable pre-relocation malloc for MPC85xxmario.six@gdsys.cc2016-04-08-0/+30
| | | | | | | | | | | | | To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch. We also make sure that the IVORs are always 4-aligned on e500 to prevent alignment exceptions caused by code changes in start.S. Signed-off-by: Mario Six <mario.six@gdsys.cc> Cc: York Sun <york.sun@nxp.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ramYork Sun2015-09-01-1/+9
| | | | | | | | | MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write through cache on E6500. L2 cache is enabled to to hold the data. This patch locks/unlocks L2 cache to ensure no data cast out from L2 cache. Signed-off-by: York Sun <yorksun@freescale.com> Reported-by: Jeffery Zhu <Jefferry.Zhu@freescale.com>
* powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041Aneesh Bansal2015-07-31-0/+11
| | | | | | | | | | | | | | | | | | | Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Use GOT when loading IVORs post-relocationScott Wood2015-05-04-15/+20
| | | | | | | | | | | | | | | | | | | | | Commit 96d2bb952bb ("powerpc/mpc85xx: Don't relocate exception vectors") simplified IVOR initialization a bit too much, failing to use the post-relocation offset. This doesn't cause a problem with normal NOR boot, in which both the pre-relocation and post-relocation addresses are 64 KiB aligned. However, if TEXT_BASE is only 4 KiB aligned, such as for NAND/SD/etc. boot on some targets, as well as the QEMU target, the post-relocation address will not be the same in the lower 16 bits, as reserve_uboot() ensures that the relocation address is always 64 KiB aligned even if the pre-relocation address was not. Use the GOT to get the proper post-relocation offsets. Fixes: 96d2bb952bb ("powerpc/mpc85xx: Don't relocate exception vectors") Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Alexander Graf <agraf@suse.de> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Tested-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Remove some dead codeScott Wood2015-04-20-137/+1
| | | | | | | | | | | | | | | | | | | U-Boot does not have system calls (the services it exposes to standalone commands use a different mechanism), so the syscall handler is dead code. It's also broken code, as it assumes it is located at 0xc00 -- while even before the patch to stop relocating exception vectors to 0, U-Boot had the syscall at 0x900. The critical and machine check return paths are never called -- the regular exception return path is used instead, which works because xSRR0/1 have already been saved and can be restored via the regular SRR0/1 (we don't care too much in U-Boot about taking a critical/mcheck inside another exception prolog/epilog). Also remove a few other small unused functions. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Don't relocate exception vectorsScott Wood2015-04-20-121/+57
| | | | | | | | | | | | | | | | Booke does not require exception vectors to be located at address zero. U-Boot was doing so anyway, simply because that's how it had been done on other PPC. The downside of this is that once the OS is loaded to address zero, the exception vectors have been overwritten -- which makes it difficult to diagnose a crash that happens after that point. The IVOR setup and trap entry code is simplified somewhat as a result. Also, there is no longer a need to align individual exceptions on 0x100 byte boundaries. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Fix boot_flag for calling board_init_f()York Sun2014-05-13-1/+1
| | | | | | | | | baord_init_f takes one argument, boot_flag. It has not been used for powerpc, until recently changing to use generic board architecture. The boot flag is added as a return value from cpu_init_f(). Signed-off-by: York Sun <yorksun@freescale.com> CC: Alexander Graf <agraf@suse.de>
* PPC 85xx QEMU: Don't use HID1Alexander Graf2014-05-13-1/+1
| | | | | | | | | | For the QEMU machine type, we can plug in either e500v2, e500mc, e5500 or e6500 style cores into the system. U-boot has to work with all of them. So avoid using HID1 which is not available on e500mc systems to make sure we don't trap on it. Signed-off-by: Alexander Graf <agraf@suse.de>
* powerpc:Add support of SPL non-relocationPrabhakar Kushwaha2014-04-22-0/+2
| | | | | | | | | | | | | Current SPL code base has BSS section placed after reset_vector. This means they have to relocate to use the global variables. This put an implicit requirement of having SPL size = Memory/2. To avoid relocation: - Move bss_section within SPL range - Modify relocate_code() Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Move LAW_EN define outside of configPrabhakar Kushwaha2014-04-22-1/+2
| | | | | | | | | | | LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence both are same. This cause compilation error. So LAW_EN define outside of configs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDSAneesh Bansal2014-04-22-1/+2
| | | | | | | | | | | | | | | | | Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: SECURE BOOT- Add secure boot target for BSC9132QDSAneesh Bansal2014-04-22-7/+2
| | | | | | | | | | Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* PPC 85xx: Add qemu-ppce500 machineAlexander Graf2014-04-22-0/+11
| | | | | | | | | | | | | | | | For KVM we have a special PV machine type called "ppce500". This machine is inspired by the MPC8544DS board, but implements a lot less features than that one. It also provides more PCI slots and is supposed to be enumerated by device tree only. This patch adds support for the generic ppce500 machine and tries to rely solely on device tree for device enumeration. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* PPC: 85xx: Remove IVOR resetAlexander Graf2014-04-22-6/+0
| | | | | | | | | | | There is no need to set IVORs to anything but their default values, so let's leave them where they are. Suggested-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Scott Wood <scottwood@freescale.com> [York Sun: Add back $(obj)start.S section in mpc8572ds/Makefile] Reviewed-by: York Sun <yorksun@freescale.com>
* Remove obsolete _LINUX_CONFIG_H macroMasahiro Yamada2014-01-24-2/+0
| | | | | | | | | Commit 643aae1406c93ddc64fcf8c136b47cdffd9c8ccd deleted include/linux/config.h but missed to delete _LINUX_CONFIG_H macro. It is no longer used at all. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc/corenet: CPC1 speculation disableDave Liu2013-12-04-0/+4
| | | | | | | | | | In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable CPC1 speculation and keep it till relocation. Otherwise, speculation transactions will go to DDR controller, it will cause problem. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2Prabhakar Kushwaha2013-10-16-1/+1
| | | | | | | | | | CHASSIS2 architecture never defines type of L2 cache present in SoC. it is dependent upon the core present in the SoC. for example, - e6500 core has L2 cluster (Kibo) - e5500 core has Backside L2 Cache Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-14-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* powerpc/mpc85xx: Add workaround for erratum A-005125York Sun2013-09-10-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | In a very rare condition, a system hang is possible when the e500 core initiates a guarded load to PCI / PCIe /SRIO performs a coherent write to memory. Please refer to errata document for more details. This erratum applies to the following SoCs and their variants, if any. BSC9132 BSC9131 MPC8536 MPC8544 MPC8548 MPC8569 MPC8572 P1010 P1020 P1021 P1022 P1023 P2020 C29x Signed-off-by: York Sun <yorksun@freescale.com> CC: Scott Wood <scottwood@freescale.com>
* powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIELiu Gang2013-08-09-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When a board (slave) boots from SRIO/PCIE, it would get the instructions from a remote board (master) by SRIO/PCIE interface, and the slave's u-boot image should be built with the SYS_TEXT_BASE=0xFFF80000; So the u-boot of the slave should avoid the NOR_BOOT branch at the booting stage. For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB entry 15 from base address "CONFIG_SYS_MONITOR_BASE & 0xffc00000", and with the 4M size as the boot window in NOR_BOOT branch. Because the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF80000, so the TLB entry will be from base address 0xffc00000 and with 4M size. Then the u-boot will set TLB entry 14 from base address "CONFIG_SYS_INIT_RAM_ADDR", and with the 16K size as the initial stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR = 0xffd00000. So the TLB entry 14 and 15 will be in confliction. There will be right TLB entries configurations when avoid the NOR_BOOT branch and set the boot window from 0xfff00000 with 1M size space. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* powerpc/mpc85xx: modify the functionality clear_bss and aligning the end ↵Ying Zhang2013-06-20-1/+1
| | | | | | | | | | | | | | | | | | | | address of the BSS There will clear the BSS in the function clear_bss(), the reset address of the BSS started from the __bss_start, and increased by four-byte increments, finally stoped depending on the address is equal to the _bss_end. If the end address __bss_end is not alignment to 4byte, it will be an infinite loop. 1. The reset action stoped depending on the reset address is greater than or equal the end address of the BSS. 2. The end address of the BSS should be 4byte aligned. Because the reset unit is 4 Bytes. This patch is on top of the patch "powerpc/mpc85xx: support application without resetvec segment in the linker script". Signed-off-by: Ying Zhang <b40530@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Clear L1 D-cache lockYork Sun2013-05-24-0/+1
| | | | | | | | dcbi instruction has been used to clear D-cache lock. However, the cache lock is persistent for e6500 core. Use dcblc to clear the lock explicitly. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Add e6500 L2 replacement policy selectionJames Yang2013-05-24-0/+1
| | | | | | | This is compile-time config. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Enable L2 cache parity/ECC error checkingJames Yang2013-05-24-1/+1
| | | | | Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* e6500: Move L1 enablement after L2 enablementAndy Fleming2013-05-14-47/+47
| | | | | | | | | | The L1 D-cache on e6500 is write-through. This means that it's not considered a good idea to have the L1 up and running if the L2 is disabled. We don't actually *use* the L1 until after the L2 is brought up on e6500, so go ahead and move the L1 enablement after that code is done. Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Add definitions for HDBCR registersAndy Fleming2013-05-14-4/+4
| | | | | | | | Makes it a bit easier to see if we've properly set them. While we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually use those definitions. Signed-off-by: Andy Fleming <afleming@freescale.com>
* Replace __bss_end__ with __bss_endSimon Glass2013-03-15-2/+2
| | | | | | | | | | | | | Note this is a tree-wide change affecting multiple architectures. At present we use __bss_start, but mostly __bss_end__. This seems inconsistent and in a number of places __bss_end is used instead. Change to use __bss_end for the BSS end symbol throughout U-Boot. This makes it possible to use the asm-generic/sections.h file on all archs. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc/mpc85xx: add support for MMUv2 page sizesScott Wood2013-01-30-1/+1
| | | | | | | | e6500 implements MMUv2 and supports power-of-2 page sizes rather than power-of-4. Add support for such pages. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* spl/powerpc: introduce CONFIG_SPL_INIT_MINIMALScott Wood2012-11-26-13/+20
| | | | | | | | | cpu_init_nand.c is renamed to spl_minimal.c as it is not really NAND-specific. Signed-off-by: Scott Wood <scottwood@freescale.com> --- v2: factor out START, and change cpu_init_nand.c to spl_minimal.c Cc: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: fix TLB alignmentScott Wood2012-11-26-4/+4
| | | | | | | | | | | | | | | In the RAMBOOT/SPL case we were creating a TLB entry starting at CONFIG_SYS_MONITOR_BASE, and just hoping that the base was properly aligned for the TLB entry size. This turned out to not be the case with NAND SPL because the main U-Boot starts at an offset into the image in order to skip the SPL itself. Fix the TLB entry to always start at a proper alignment. We still assume that CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary thus requiring multiple TLB entries. Signed-off-by: Scott Wood <scottwood@frescale.com> Cc: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: move debug tlb entry after TLB is in known stateScott Wood2012-11-26-44/+40
| | | | | | | | | | | | Previously, in many if not all configs we were creating overlapping TLB entries which is illegal. This caused a crash during boot when moving p2020rdb NAND SPL into L2 SRAM. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Andy Fleming <afleming@freescale.com> -- Prabhakar, please test that debug still works.
* powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500York Sun2012-10-22-1/+36
| | | | | | | | | | | | | Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Introduce new macros to add and delete TLB entriesYork Sun2012-10-22-179/+130
| | | | | | | These assembly macros simplify codes to add and delete temporary TLB entries. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: clear out TLB on bootScott Wood2012-08-23-33/+43
| | | | | | | | Instead of just shooting down the entry that covers CCSR, clear out every TLB entry that isn't the one that we're executing out of. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/fsl-corenet: work around erratum A004510Scott Wood2012-08-23-0/+284
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A004510 says that under certain load conditions, modified cache lines can be discarded, causing data corruption. To work around this, several CCSR and DCSR register updates need to be made in a careful manner, so that there is no other transaction in corenet when the update is made. The update is made from a locked cacheline, with a delay before to flush any previous activity, and a delay after to flush the CCSR/DCSR update. We can't use a readback because that would be another corenet transaction, which is not allowed. We lock the subsequent cacheline to prevent it from being fetched while we're executing the previous cacheline. It is filled with nops so that a branch doesn't cause us to fetch another cacheline. Ordinarily we are running in a cache-inhibited mapping at this point, so we temporarily change that. We make it guarded so that we should never see a speculative load, and we never do an explicit load. Thus, only the I-cache should ever fill from this mapping, and we flush/unlock it afterward. Thus we should avoid problems from any potential cache aliasing between inhibited and non-inhibited mappings. NOTE that if PAMU is used with this patch, it will need to use a dedicated LAW as described in the erratum. This is the responsibility of the OS that sets up PAMU. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mpc85xx: Initial SP alignment is wrong.Joakim Tjernlund2012-08-22-11/+5
| | | | | | | | | | | | PowerPC mandates SP to be 16 bytes aligned. Furthermore, a stack frame is added, pointing to the reset vector which may in the way when gdb is walking the stack because the reset vector may not accessible depending on emulator settings. Also use a temp register so gdb doesn't pick up intermediate values. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx:Fix NAND code base to support debuggerPrabhakar Kushwaha2012-07-06-1/+1
| | | | | | | | | | | | Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR + IVOR15 should be valid fetchable OP code address. As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to any fetchable valid data Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* powerpc/85xx:Make debug exception vector accessiblePrabhakar Kushwaha2012-07-06-5/+78
| | | | | | | | | | | | | | | | | | | Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR + IVOR15) to have valid and fetchable OP code. 1) While executing in translated space (AS=1), whenever a debug exception is generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to fetch an instruction from the debug exception vector (IVPR + IVOR15); since now we are in AS=0, the application needs to ensure the proper TLB configuration to have (IVOR + IVOR15) accessible from AS=0 also. Create a temporary TLB in AS0 to make sure debug exception verctor is accessible on debug exception. 2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* powerpc/85xx:Fix MSR[DE] bit in MSR to support debuggerPrabhakar Kushwaha2012-07-06-2/+5
| | | | | | | | | | | | | Debugging of e500 and e500v1 processer requires MSR[DE] bit to be set always. Where MSR = Machine State register Make sure of MSR[DE] bit is set uniformaly across the different execution address space i.e. AS0 and AS1. Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Catalin Udma <catalin.udma@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSRTimur Tabi2012-04-24-2/+6
| | | | | | | The CCSR relocation code in start.S writes to MAS7 on all e500 parts, but that register does not exist on e500v1. Signed-off-by: Timur Tabi <timur@freescale.com>
* powerpc/85xx:Avoid vector table compilation for nand_splPrabhakar Kushwaha2012-04-24-0/+6
| | | | | | | | NAND SPL code never compile the vector table. So no need to setup interrupt vector table for NAND SPL. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx:Fix IVORs addr after vector table relocationPrabhakar Kushwaha2012-04-24-0/+33
| | | | | | | | | | | After relocation of vector table in SDRAM's lower address, IVORs value should be updated with new handler addresses. As vector tables are relocated to 0x100,0x200... 0xf00 address in DDR.IVORs are updated with 0x100, 0x200,....f00 hard-coded values. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx:Avoid hardcoded vector address for IVORsPrabhakar Kushwaha2012-04-24-31/+34
| | | | | | | | | | | | For e500 and e500v2 architecturees processor IVPR address should be alinged on 64K boundary. in start.S, CONFIG_SYS_MONITOR_BASE is stored blindly in IVPR assuming it to be 64K aligned. It may not be true always. If it is not aligned, IVPR + IVORs may not point to an exception handler. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: Add workaround for erratum CPU-A003999Kumar Gala2011-11-29-0/+6
| | | | | | | | | | | | | | | | | Erratum A-003999: Running Floating Point instructions requires special initialization. Impact: Floating point arithmetic operations may result in an incorrect value. Workaround: Perform a read modify write to set bit 7 to a 1 in SPR 977 before executing any floating point arithmetic operation. This bit can be set when setting MSR[FP], and can be cleared when clearing MSR[FP]. Alternatively, the bit can be set once at boot time, and never cleared. There will be no performance degradation due to setting this bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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