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* mips: Drop unused code in u-boot.hSimon Glass2016-05-27-16/+0
| | | | | | | Since generic board init is enabled, this is not used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: ath79: ar933x: Avoid warning with gcc5Wills Wang2016-05-26-0/+2
| | | | | | | | GCC 5.3 report a warning: 'upper' and 'lower' may be used uninitialized in this function [-Wmaybe-uninitialized]. Compiler might need explicit initializer. Signed-off-by: Wills Wang <wills.wang@live.com>
* mips: ath79: ar933x: Fix ethernet PHY mismatchWills Wang2016-05-26-1/+3
| | | | | | | | We need reset the Ethernet Switch analog part before operation, or the build-in Ethernet PHY don't work. Signed-off-by: Wills Wang <wills.wang@live.com> Acked-by: Marek Vasut <marex@denx.de>
* mips: Drop JZ4740 remnantsMarek Vasut2016-05-26-1158/+0
| | | | | | | | Remove the remnants of JZ4740 support. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
* mips: Allow overriding start.S in SPLMarek Vasut2016-05-26-0/+6
| | | | | | | | | | Certain chips, like the JZ47xx, have extreme size constraints on the SPL size and require custom start.S . Allow overriding the start.S the same way ARM MXS does it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
* malta: Use device model & tree for UARTPaul Burton2016-05-26-0/+37
| | | | | | | | | | | Make use of device model & device tree to probe the UART driver. This is the initial step in bringing Malta up to date with driver model, and allows for cleaner handling of the different I/O addresses for different system controllers by specifying the ISA bus address instead of a translated memory address. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* malta: Support MIPS32r6 configurationsPaul Burton2016-05-21-0/+1
| | | | | | | | Both real Malta boards & QEMU's Malta emulation can feature MIPS32r6 CPUs. Allow building U-Boot for such systems by selecting CONFIG_SUPPORTS_CPU_MIPS32_R6 for Malta. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Support for targetting MIPSr6Paul Burton2016-05-21-6/+30
| | | | | | | | | | | Add support for targetting MIPS32r6 & MIPS64r6 systems, in the same way that we currently select release 1 or release 2 targets. MIPSr6 is not entirely backwards compatible with earlier releases of the architecture. Some instructions are encoded differently, some are removed, some are reused, so it is not practical to run U-Boot built for earlier revisions on a MIPSr6 system. Update their Kconfig help text to reflect that. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Simplify CONFIG_SYS_CPU valuesPaul Burton2016-05-21-2/+2
| | | | | | | | | | | | Rather than having the values for CONFIG_SYS_CPU depend upon each architecture revision, have them depend upon the more general CONFIG_CPU_MIPS32 & CONFIG_CPU_MIPS64 which in turn depend upon the architecture revisions. This is done in preparation for adding MIPSr6 support, which would otherwise need to introduce new cases here. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Use unchecked immediate addition/subtractionPaul Burton2016-05-21-11/+13
| | | | | | | | | | | | In MIPS assembly there have historically been 2 variants of immediate addition - the standard "addi" which traps if an overflow occurs, and the unchecked "addiu" which does not trap on overflow. In release 6 of the MIPS architecture the trapping variants of immediate addition & subtraction have been removed. In preparation for supporting MIPSr6, stop using the trapping instructions from assembly & switch to their unchecked variants. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* mips: ath79: Add support for TPLink WDR4300Marek Vasut2016-05-21-0/+59
| | | | | | | | | | Add support for the TPLink WDR4300 router, which is based on the AR9344 MIPS 74Kc CPU and has 128 MiB of RAM. The USB is supported on this system as well. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
* mips: ath79: Add AR934x supportMarek Vasut2016-05-21-1/+683
| | | | | | | | | | Add support for the Atheros AR934x WiSoCs. This patchs adds complete system init, including PLL and DRAM init, both of which happen from full C environment, since the AR934x has proper SRAM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
* mips: ath79: Add support for ungating ethernet on ar933x and ar934xMarek Vasut2016-05-21-0/+80
| | | | | | | | Add code to ungate the ethernet controller on ar933x and ar934x . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
* mips: ath79: dts: Add ethernet MAC nodes for ar933xMarek Vasut2016-05-21-0/+26
| | | | | | | | | Add node for both ethernet controllers in the ar933x. The PHY is attached only to the first ethernet controller. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
* mips: ath79: Add support for ungating USB on ar933x and ar934xMarek Vasut2016-05-21-0/+61
| | | | | | | | Add code to ungate the USB controller on ar933x and ar934x . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
* mips: ath79: dts: Add generic-ehci nodeMarek Vasut2016-05-21-0/+7
| | | | | | | | Add generic EHCI node for the ChipIdea EHCI controller in the ath79. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
* mips: ath79: Fix compiler warning on const assignmentMarek Vasut2016-05-21-1/+1
| | | | | | | | | The assignment const T var; var = value; is illegal, since var is constant. Drop the const to fix the compiler warning. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
* mips: ath79: Fix ar71xx_regs.h indentMarek Vasut2016-05-21-1034/+1069
| | | | | | | | | The indent in this file triggers my OCD, so fix it. Replace multiple spaces with tabs and align the values in one column. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
* mips: Add MIPS 74Kc tuneMarek Vasut2016-05-21-0/+4
| | | | | | | | | | Add MIPS 74Kc tune Kconfig option. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com> [added missing tune-y entry in arch/mips/Makefile] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: Fix compiler warning in cpu.cMarek Vasut2016-05-21-1/+0
| | | | | | | | | | | | | | | There really is zero reason for including netdev.h in generic mips CPU code. Removing the netdev.h from cpu.c also fixes the following compiler warning: In file included from arch/mips/cpu/cpu.c:10:0: include/netdev.h:204:41: warning: 'struct eth_device' declared inside parameter list [enabled by default] int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)); ^ include/netdev.h:204:41: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default] Signed-off-by: Marek Vasut <marex@denx.de> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* ath79: add readonly attribute for ath79_soc_descWills Wang2016-05-21-4/+4
| | | | | | use 'const' keywork to qualify readonly attribute for lookup-table member Signed-off-by: Wills Wang <wills.wang@live.com>
* ath79: ar933x: use BIT macro for bit shift operationWills Wang2016-05-21-7/+7
| | | | | | used a uniform BIT macro for register bit-field shift Signed-off-by: Wills Wang <wills.wang@live.com>
* mips: ath79: add AP143 reference boardWills Wang2016-05-21-0/+133
| | | | | | | | This patch add board-level code and base DT for AP143. Signed-off-by: Wills Wang <wills.wang@live.com> [updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: ath79: add AP121 reference boardWills Wang2016-05-21-0/+137
| | | | | | | | This patch add board-level code and base DT for AP121. Signed-off-by: Wills Wang <wills.wang@live.com> [updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: ath79: add support for QCA953x SOCsWills Wang2016-05-21-1/+787
| | | | | | This patch enable work for qca953x SOC. Signed-off-by: Wills Wang <wills.wang@live.com>
* mips: ath79: add support for AR933x SOCsWills Wang2016-05-21-0/+720
| | | | | | This patch enable work for ar933x SOC. Signed-off-by: Wills Wang <wills.wang@live.com>
* mips: add base support for QCA/Atheros ath79 SOCsWills Wang2016-05-21-0/+1610
| | | | | | | This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection. Signed-off-by: Wills Wang <wills.wang@live.com>
* Fix various typos, scattered over the code.Robert P. J. Day2016-05-05-1/+1
| | | | | | | | | | | | | Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller
* MIPS: bootm: Add fixup of '/memory' node.Purna Chandra Mandal2016-04-19-2/+3
| | | | | | | | | | | | MIPS arch do not update 'reg' property of /memory node. As a result Linux bootup will not work unless board.dts file contains right /memory offset-size information or board implements required memory fixup. Fixing by renaming (unused) _arch_fixup_memory_node_ to _arch_fixup_fdt_ in arch/mips/lib/bootm.c inline with ARM arch. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* board: pic32mzda: enable USB-host, USB-storage support.Purna Chandra Mandal2016-04-10-0/+16
| | | | | | | Enable MUSB host and USB storage support for Microchip PIC32MZ[DA] Starter Kit. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
* MIPS: fix mips_cache fallback without __builtin_mips_cacheMatthias Schiffer2016-03-09-1/+1
| | | | | | | | | | | The "R" constraint supplies the address of an variable in a register. Use "r" instead and adjust asm to supply the content of addr in a register instead. Fixes: 2b8bcc5a ("MIPS: avoid .set ISA for cache operations") Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Use correct spelling of "U-Boot"Bin Meng2016-02-06-1/+1
| | | | | | | | | | Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* board: Enable ethernet, tftpboot support to pic32mzdask board.Purna Chandra Mandal2016-02-01-0/+20
| | | | | | | This adds ethernet, TFTP support for PIC32MZ[DA] Starter Kit. Also custom environment variables/scripts are added to help boot from network. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
* board: add SDHCI support for PIC32MZDASK board.Purna Chandra Mandal2016-02-01-0/+18
| | | | | | | Enable MMC, SDHCI, FAT_FS support for PIC32MZ[DA] StarterKit. Also add custom scripts, rules to boot Linux from microSD card. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
* board: Add Microchip PIC32MZ[DA]-Starter-Kit board.Purna Chandra Mandal2016-02-01-1/+52
| | | | | | | | This adds support for Microchip PIC32MZ[DA] StarterKit board based on a PIC32MZ[DA] family of microcontroller. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: Add support for Microchip PIC32MZ[DA] SoC family.Purna Chandra Mandal2016-02-01-2/+379
| | | | | | | Add Microchip PIC32MZ[DA] SoC family support. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+32
| | | | | | | | | | | This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module. DDR2 controller operates in half-rate mode (upto 533MHZ frequency). Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* MIPS: initial infrastructure for Microchip PIC32 architecturePurna Chandra Mandal2016-02-01-0/+110
| | | | | | | | | Create initial directory, Kconfigs needed for PIC32 architecture support. Also add PIC32 specific register definition required for drivers. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* MIPS: Support dynamic I/O port base addressPaul Burton2016-02-01-34/+34
| | | | | | | | | | | | The existing mips_io_port_base variable isn't suitable for use early during boot since it will be stored in the .data section which may not be writable pre-relocation. Fix this by moving the I/O port base address into struct arch_global_data. In order to avoid adding this field for all targets, make this dependant upon a new Kconfig entry CONFIG_DYNAMIC_IO_PORT_BASE. Malta is the only board which sets a non-zero I/O port base, so select this option only for Malta. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Remove SLOW_DOWN_IOPaul Burton2016-02-01-37/+3
| | | | | | | | | CONF_SLOWDOWN_IO is never set for any target, so remove the dead code in the SLOW_DOWN_IO macro. This is done in preparation for changes to mips_io_port_base which can be avoided in this path by removing it entirely. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* mips: cache: Bulletproof the code against cornercasesMarek Vasut2016-02-01-0/+8
| | | | | | | | | | | | | | | | | | | This patch makes sure that the flush/invalidate_dcache_range() functions can handle corner-case calls like this -- invalidate_dcache_range(0, 0, 0); This call is valid and is happily produced by USB EHCI code for example. The expected behavior of the cache function(s) in this case is that they will do no operation, since the size is zero. The current implementation though has a problem where such invocation will result in a hard CPU hang. This is because under such conditions, where the start_addr = 0 and stop = 0, the addr = 0 and aend = 0xffffffe0 . The loop will then try to iterate over the entire address space, which in itself is wrong. But iterating over the entire address space might also hit some odd address which will cause bus hang. The later happens on the Atheros MIPS. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Hans de Goede <hdegoede@redhat.com>
* MIPS: start.S: fix and optimize instructionsDaniel Schwierzeck2016-02-01-11/+11
| | | | | | | | Fix 32 vs 64 bit load/store instructions. Access CP0_WATCHHI as 32 Bit register. Use 64 Bit register access for clearing gd_data and copying U-Boot. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: initialize board_init_f() argument to zero.Purna Chandra Mandal2016-02-01-1/+1
| | | | | | | | | Argument boot_flags of board_init_f() should be set to 0 as $a0 may be utilized in lowlevel_init() or mips_cache_reset() or previous stage boot-loader. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: asm/io.h: Add in <linux/bug.h>Tom Rini2016-01-25-0/+1
| | | | | | As part of the bug.h / BUILD_BUG_* clean up, this file was missed. Signed-off-by: Tom Rini <trini@konsulko.com>
* MIPS: implement bit manipulating I/O accessorsDaniel Schwierzeck2016-01-16-0/+55
| | | | | | | Add support for functions clrbits_X(), setbits_X() and clrsetbits_X() on MIPS. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: fix SPDX license identifier in remaining arch header filesDaniel Schwierzeck2016-01-16-55/+32
| | | | | | | Add a SPDX license identifier to MIPS header files where it is still missing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: sync processor and register definitions with linux-4.4Daniel Schwierzeck2016-01-16-553/+1211
| | | | | | | Update definitions for processor, registers as well as assemby macros. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: sync I/O related header files with linux-4.4Daniel Schwierzeck2016-01-16-364/+941
| | | | | | | | | | | | | Mainly sync asm/io.h to get a working ioremap() implementation as well as the full set of I/O accessors. Pull in additional header files to make this work. Furthermore port over the directory 'arch/mips/include/asm/mach-generic/' with contains default definitions for I/O and memory spaces and default implementations for mapping those spaces. All files in that directory can be overwritten by a SoC/machine. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: kconfig: add option for MIPS_L1_CACHE_SHIFTDaniel Schwierzeck2016-01-16-10/+25
| | | | | | | | | | | | | | | | Add Kconfig symbol for L1 cache shift like the kernel does. The value of CONFIG_SYS_CACHELINE_SIZE is not a reliable source for ARCH_DMA_MINALIGN anymore, because it is optional on MIPS. If CONFIG_SYS_CACHELINE_SIZE is not defined by a board, the cache sizes are automatically detected and ARCH_DMA_MINALIGN would be set to 128 Bytes. The default value for CONFIG_MIPS_L1_CACHE_SHIFT is 5 which corresponds to 32 Bytes. All current MIPS boards already used that value. While on it, fix the Malta board to use a value of 6 like the kernel port does. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: Kconfig: optimize gcc -march and -mtune setupDaniel Schwierzeck2016-01-16-15/+24
| | | | | | | | Move setup of -march to arch/mips/Makefile and follow the design on ARM. Also add a possibility to chose specific CPU tune options. Signed-off-by: Wills Wang <wills.wang@live.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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