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* Remove arch/${ARCH}/include/asm/errno.hMasahiro Yamada2016-09-23-1/+0
| | | | | | | | | | | | | | Unlike Linux, nothing about errno.h is arch-specific in U-Boot. As you see, all of arch/${ARCH}/include/asm/errno.h is just a wrapper of <asm-generic/errno.h>. Actually, U-Boot does not export headers to user-space, so we just have to care about the consistency in the U-Boot tree. Now all of include directives for <asm/errno.h> are gone. Deprecate <asm/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
* MIPS: Hang if run on a secondary CPUPaul Burton2016-09-21-0/+7
| | | | | | | | | | | | | Some systems are configured such that multiple CPUs begin running from their reset vector following a system reset. If this occurs then U-Boot will be run on multiple CPUs simultaneously, which causes all sorts of issues as the multiple instances of U-Boot clobber each other. Prevent this from happening by simply hanging with an infinite loop if we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum as appropriate, is non-zero. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Join the coherent domain when a CM is presentPaul Burton2016-09-21-0/+5
| | | | | | | | | | | MIPS Linux expects the bootloader to leave the boot CPU a member of the coherent domain when running on a system with a CM, and we will need to do so if we wish to make use of IOCUs to have cache-coherent DMA in U-Boot (and on some systems there is no choice in that matter). When a CM is present, join the coherent domain after completing cache initialisation. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: L2 cache supportPaul Burton2016-09-21-0/+46
| | | | | | | | | | | | | | | This patch adds support for initialising & maintaining L2 caches on MIPS systems. The L2 cache configuration may be advertised through either coprocessor 0 or the MIPS Coherence Manager depending upon the system, and support for both is included. If the L2 can be bypassed then we bypass it early in boot & initialise the L1 caches first, such that we can start making use of the L1 instruction cache as early as possible. Otherwise we initialise the L2 first such that the L1s have no opportunity to generate access to the uninitialised L2. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Map CM Global Control RegistersPaul Burton2016-09-21-0/+19
| | | | | | | Map the Global Control Registers (GCRs) provided by the MIPS Coherence Manager (CM) in preparation for using some of them in later patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Preserve Config implementation-defined bitsPaul Burton2016-09-21-0/+1
| | | | | | | | | | The coprocessor 0 Config register includes 9 implementation defined bits, which in some processors do things like enable write combining or other functionality. We ought not to wipe them to 0 during boot. Rather than doing so, preserve their value & only clear the bits standardised by the MIPS architecture. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Probe cache line sizes once during bootPaul Burton2016-09-21-0/+13
| | | | | | | | | | | Rather than probing the cache line sizes on every call of any cache maintenance function, probe them once during boot & store the values in the global data structure for later use. This will reduce the overhead of the cache maintenance functions, which isn't a big deal yet but becomes more important once L2 caches which may expose their properties via coprocessor 2 or the CM are supported. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Split I & D cache line size configPaul Burton2016-05-31-0/+7
| | | | | | | | | | | | Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: remove dead code from asm/u-boot-mips.hDaniel Schwierzeck2016-05-31-18/+3
| | | | | | | | Those wrappers for linker symbols were once used in the MIPS specific board.c implementation. Since the migration to generic board.c, those wrappers are dead code and can be removed. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: Use CPHYSADDR to implement mips32 virt_to_physPaul Burton2016-05-31-4/+1
| | | | | | | | | | | | | | | | | | Use CPHYSADDR to implement the virt_to_phys function for converting from a virtual to a physical address for MIPS32, much as is already done for MIPS64. This allows for virt_to_phys to work regardless of whether the address being translated is in kseg0 or kseg1, unlike the previous subtraction based approach which only worked for addresses in kseg0. This allows for drivers to provide an address to virt_to_phys without needing to manually ensure that kseg1 addresses are converted to equivalent kseg0 addresses first. This patch is equivalent to this Linux patch currently waiting to be reviewed & merged: https://patchwork.linux-mips.org/patch/12564/ Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* mips: Drop unused code in u-boot.hSimon Glass2016-05-27-16/+0
| | | | | | | Since generic board init is enabled, this is not used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: Drop JZ4740 remnantsMarek Vasut2016-05-26-1158/+0
| | | | | | | | Remove the remnants of JZ4740 support. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
* mips: add base support for QCA/Atheros ath79 SOCsWills Wang2016-05-21-0/+6
| | | | | | | This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection. Signed-off-by: Wills Wang <wills.wang@live.com>
* MIPS: fix mips_cache fallback without __builtin_mips_cacheMatthias Schiffer2016-03-09-1/+1
| | | | | | | | | | | The "R" constraint supplies the address of an variable in a register. Use "r" instead and adjust asm to supply the content of addr in a register instead. Fixes: 2b8bcc5a ("MIPS: avoid .set ISA for cache operations") Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: Support dynamic I/O port base addressPaul Burton2016-02-01-21/+30
| | | | | | | | | | | | The existing mips_io_port_base variable isn't suitable for use early during boot since it will be stored in the .data section which may not be writable pre-relocation. Fix this by moving the I/O port base address into struct arch_global_data. In order to avoid adding this field for all targets, make this dependant upon a new Kconfig entry CONFIG_DYNAMIC_IO_PORT_BASE. Malta is the only board which sets a non-zero I/O port base, so select this option only for Malta. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Remove SLOW_DOWN_IOPaul Burton2016-02-01-37/+3
| | | | | | | | | CONF_SLOWDOWN_IO is never set for any target, so remove the dead code in the SLOW_DOWN_IO macro. This is done in preparation for changes to mips_io_port_base which can be avoided in this path by removing it entirely. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* mips: asm/io.h: Add in <linux/bug.h>Tom Rini2016-01-25-0/+1
| | | | | | As part of the bug.h / BUILD_BUG_* clean up, this file was missed. Signed-off-by: Tom Rini <trini@konsulko.com>
* MIPS: implement bit manipulating I/O accessorsDaniel Schwierzeck2016-01-16-0/+55
| | | | | | | Add support for functions clrbits_X(), setbits_X() and clrsetbits_X() on MIPS. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: fix SPDX license identifier in remaining arch header filesDaniel Schwierzeck2016-01-16-55/+32
| | | | | | | Add a SPDX license identifier to MIPS header files where it is still missing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: sync processor and register definitions with linux-4.4Daniel Schwierzeck2016-01-16-543/+1201
| | | | | | | Update definitions for processor, registers as well as assemby macros. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: sync I/O related header files with linux-4.4Daniel Schwierzeck2016-01-16-363/+937
| | | | | | | | | | | | | Mainly sync asm/io.h to get a working ioremap() implementation as well as the full set of I/O accessors. Pull in additional header files to make this work. Furthermore port over the directory 'arch/mips/include/asm/mach-generic/' with contains default definitions for I/O and memory spaces and default implementations for mapping those spaces. All files in that directory can be overwritten by a SoC/machine. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: kconfig: add option for MIPS_L1_CACHE_SHIFTDaniel Schwierzeck2016-01-16-10/+4
| | | | | | | | | | | | | | | | Add Kconfig symbol for L1 cache shift like the kernel does. The value of CONFIG_SYS_CACHELINE_SIZE is not a reliable source for ARCH_DMA_MINALIGN anymore, because it is optional on MIPS. If CONFIG_SYS_CACHELINE_SIZE is not defined by a board, the cache sizes are automatically detected and ARCH_DMA_MINALIGN would be set to 128 Bytes. The default value for CONFIG_MIPS_L1_CACHE_SHIFT is 5 which corresponds to 32 Bytes. All current MIPS boards already used that value. While on it, fix the Malta board to use a value of 6 like the kernel port does. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: au1x00: move SoC header files to arch/mips/mach-au1x00/include/mach/Daniel Schwierzeck2016-01-16-1072/+0
| | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: create .text sub-sections for assembler functionsDaniel Schwierzeck2016-01-16-1/+3
| | | | | | | | Put all functions coded in assembly in sub-sections of section .text. This allows the linker to garbage collect unused assembly functions too. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: fix annotation of _start and relocate_codeDaniel Schwierzeck2016-01-16-0/+6
| | | | | | | Correctly annotate _start and relocate_code as functions to produce more readable disassembly code generated by objdump. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: add asm/gpio.h to fix compilation error with CONFIG_CMD_GPIO.Purna Chandra Mandal2016-01-16-0/+1
| | | | | | | | | | With CONFIG_CMD_GPIO compilation reports error. common/cmd_gpio.c:13:22: fatal error: asm/gpio.h: No such file or directory #include <asm/gpio.h> ^ Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Chin Liang See <clsee@altera.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mips: Use the generic bitops headersFabio Estevam2015-11-05-0/+5
| | | | | | | | The generic bitops headers are required when calling logarithmic functions, such as ilog2(). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: Use unsigned int when reading c0 registersChris Packham2015-08-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit a18a477 (MIPS: use common code from lib/time.c) MIPS platforms started using common the common timer functions which are based around the fact that many platforms have a 32-bit free running counter register that can be used see commit 8dfafdd (Introduce common timer functions). Even MIPS64 has such a 32-bit register (some have an additional 64-bit free running counter, but that's something for another time). The problem is that in __read_32bit_c0_register() we read the value from this register into an _signed_ int and as it's returned up the call chain to timer_read_counter() it gets assigned to an unsigned long. On a 32-bit system there is no problem. On a 64-bit system odd things happen, sign extension seems to kick in and all of a sudden if the counter register happens to have the MSb (i.e. the sign bit) set the negative int gets sign extended into a very large unsigned long value. This in turn throws out things from get_ticks() up. Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to use "unsigned int res;" instead of "int res;". There seems to be little reason to treat these register values as signed. They are either counters (which by definition are unsigned) or are made up of various bit fields to be interpreted as per the CPU datasheet. Reported-by: Sachin Surendran <sachin.surendran@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com>
* MIPS: change 'extern inline' to 'static inline'Daniel Schwierzeck2015-07-02-9/+9
| | | | | | | | The kernel changed it a long time ago. Also this is now broken on gcc-5.x. Reported-by: Andy Kennedy <andy.kennedy@adtran.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: fix missing semicolon in cacheops.hTony Wu2015-07-02-1/+1
| | | | | | | | Fix missing semicolon in cacheops.h introduced in commit 2b8bcc5a2 (MIPS: avoid .set ISA for cache operations) Signed-off-by: Tony Wu <tung7970@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
* malta: IDE supportPaul Burton2015-01-29-0/+5
| | | | | | | | | This patch adds IDE support to the MIPS Malta board. The IDE controller is enabled after probing the PCI bus and otherwise just makes use of U-boot generic IDE support. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: avoid .set ISA for cache operationsPaul Burton2015-01-29-0/+13
| | | | | | | | | | | | As a step towards unifying the cache maintenance code for mips32 & mips64 CPUs, stop using ".set <ISA>" directives in the more developed mips32 version of the code. Instead, when present make use of the GCC builtin for emitting a cache instruction. When not present, simply don't bother with the .set directives since U-boot always builds with -march=mips32 or higher anyway. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: add support for pre-relocation mallocDaniel Schwierzeck2015-01-21-2/+0
| | | | | | | | | | | Implement MIPS specific setup of the gd_t structure to support pre-relocation malloc. If CONFIG_SYS_MALLOC_F_LEN is specified, a memory area will be reserved after the initial stack area and the gd->malloc_base pointer will be initialized. After this patch the new driver model can be used on MIPS. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Replace <compiler.h> with <linux/compiler.h>Masahiro Yamada2014-12-08-1/+1
| | | | | | Including <linux/compiler.h> is enough for general use. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* common/board_f: Initialized global data for generic boardYork Sun2014-05-12-0/+2
| | | | | | | | | | | | | Some platforms (tested on mpc85xx, mpc86xx) use global data before calling function baord_inti_f(). The data should not be cleared later. Any arch which uses global data in generic board board_init_f() should define CONFIG_SYS_GENERIC_GLOBAL_DATA. Signed-off-by: York Sun <yorksun@freescale.com> CC: Scott Wood <scottwood@freescale.com> CC: Simon Glass <sjg@chromium.org> CC: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Simon Glass <sjg@chromium.org>
* bd_info: remove bi_barudrate member from struct bd_infoMasahiro Yamada2014-05-12-1/+0
| | | | | | | | | | | | | | | | | gd->bd->bi_baudrate is a copy of gd->baudrate. Since baudrate is a common feature for all architectures, keep gd->baudrate only. It is true that bi_baudrate was passed to the kernel in that structure but it was a long time ago. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Cc: Simon Glass <sjg@chromium.org> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de> Acked-by: Michal Simek <monstr@monstr.eu> (For microblaze)
* MIPS: drop incaip boardDaniel Schwierzeck2014-04-20-2432/+0
| | | | | | | | | This is dead hardware and no one is interested in making the necessary changes for upcoming features like generic board or driver model. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wolfgang Denk <wd@denx.de>
* MIPS: allow use of generic boardPaul Burton2014-04-20-0/+9
| | | | | | | | This patch allows MIPS boards to make use of generic board, replacing arch/mips/lib/board.c with common/board_{f,r}.c and struct bd_info with the asm-generic version. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: fix types u64 and __u64 to unsigned long longDaniel Schwierzeck2014-03-04-20/+3
| | | | | | | | Linux MIPS uses asm-generic/int-ll64.h in asm/types.h. Thus u64 and __u64 are defined as unsigned long long. Port this over to U-Boot. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* malta: enable PIIX4 SERIRQPaul Burton2013-11-26-0/+7
| | | | | | | | | | | | | Whilst U-boot does not require this itself, Linux currently relies upon it having been muxed and enabled by the bootloader. Thus in order to preserve compatibility with current kernels before a fix is merged in Linux we will enable the SERIRQ interrupt and mux it to its pin. Without doing this current kernels will never receive serial port interrupts and the end result is typically that userland appears to hang. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* malta: use unmapped flash base addressGabor Juhos2013-11-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The physical base address of the NOR flash is 0x1e000000 on the Malta boards. The hardware also maps the first 4MiB of the flash into the 0x1fc00000-0x1fffffff range. Currently, U-Boot uses the mapped address to access the flash, which does not work in recent qemu versions. Since commit a427338b222b43197c2776cbc996936df0302f51 (mips_malta: correct reading MIPS revision at 0x1fc00010) writing to the mapped address space causes a CPU exception. Due to the exception, U-Boot hangs during boot when it tries to detect the CFI flash chip. Use the correct physical address for the MALTA_FLASH_BASE constant to fix the problem. In order to avoid relocation problems, also update the CONFIG_SYS_{TEXT,MONITOR}_BASE constants. The change makes it possible to start U-Boot on a Malta board emulated with Qemu 1.6.1 and 1.7.0-rc0. It also works on older versions (tested with 1.1.1, 1.2.2, 1.4.2, 1.5.3). Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
* malta: arch/mips/include/asm/malta.h SPDX license tagPaul Burton2013-11-11-3/+2
| | | | | | | | This patch replaces the GPL-2.0 text with a GPL-2.0 SPDX-License-Identifier tag, and adds Imagination Technologies copyright following my recent changes. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* malta: setup PIIX4 interrupt routePaul Burton2013-11-09-0/+5
| | | | | | | | | | | | Without setting up the PIRQ[A:D] interrupt routes, PCI interrupts will be left disabled. Linux does not set up this routing but relies upon it having been set up by the bootloader, reading back the IRQ lines which the PIRQ[A:D] signals have been routed to. This patch routes PIRQA & PIRQB to IRQ 10, and PIRQC & PIRQD to IRQ 11. This matches the setup used by YAMON. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* malta: display "U-boot" on the LCD screenPaul Burton2013-11-09-0/+10
| | | | | | | Displaying a message on the LCD screen is a simple yet effective way to show the user that the board has booted successfully. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* malta: support for coreFPGA6 boardsPaul Burton2013-11-09-6/+29
| | | | | | | | | | | | | | | | | | | | | This patch adds support for running on Malta boards using coreFPGA6 core cards, including support for the msc01 system controller used with them. The system controller is detected at runtime allowing one U-boot binary to run on a Malta with either. Due to the PCI I/O base differing between Maltas using gt64120 & msc01 system controllers, the UART setup is modified slightly. A second UART is added so that there is one pointing at the correct address for each system controller. The Malta board then defines its own default_serial_console function to select the correct one at runtime. The incorrect UART will simply not function. Tested on: - A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both with and without an L2 cache. - QEMU. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* mips32: detect L1 cache sizes if they're not definedPaul Burton2013-11-09-0/+6
| | | | | | | | | | | | | | | | For boards such as the MIPS Malta with an FPGA core card it is desirable to be able to detect the L1 cache sizes at runtime, since they are not dependant upon the board but on the FPGA bitstream in use. This patch performs that detection when the CONFIG_SYS_[DI]CACHE_SIZE macros are not defined by the board configuration. In cases where the sizes are detected this patch also removes the restriction that the I-cache & D-cache line sizes must be the same, as this is not necessarily true. If the cache sizes are defined by a configuration then they will be hardcoded as before, so this patch will not add overhead to such boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* include: delete include/linux/config.hMasahiro Yamada2013-11-08-5/+0
| | | | | | | | | | | | Linux Kernel abolished include/linux/config.h long time ago. (around version v2.6.18..v2.6.19) We don't need to provide Linux copatibility any more. This commit deletes include/linux/config.h and fixes source files not to include this. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* cosmetic: remove empty lines at the top of fileMasahiro Yamada2013-11-08-1/+0
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* MIPS: bootm: add support for generic relocation of init ramdisksDaniel Schwierzeck2013-08-13-0/+1
| | | | | | | | All linux kernels after v2.6 require a page-aligned location of an external init ramdisk. Enable CONFIG_SYS_BOOT_RAMDISK_HIGH to support this with the generic U-Boot relocation code. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: bootm: add support for LMBDaniel Schwierzeck2013-08-13-0/+2
| | | | | | | | This is required for init ramdisk relocation and device tree support. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
generated by cgit v1.1 at 2024-11-02 15:53:23 +0000