| Commit message (Collapse) | Author | Age | Lines | |
|---|---|---|---|---|
| * | MIPS: kconfig: add option for MIPS_L1_CACHE_SHIFT | Daniel Schwierzeck | 2016-01-16 | -10/+4 |
| | | | | | | | | | | | | | | | | | Add Kconfig symbol for L1 cache shift like the kernel does. The value of CONFIG_SYS_CACHELINE_SIZE is not a reliable source for ARCH_DMA_MINALIGN anymore, because it is optional on MIPS. If CONFIG_SYS_CACHELINE_SIZE is not defined by a board, the cache sizes are automatically detected and ARCH_DMA_MINALIGN would be set to 128 Bytes. The default value for CONFIG_MIPS_L1_CACHE_SHIFT is 5 which corresponds to 32 Bytes. All current MIPS boards already used that value. While on it, fix the Malta board to use a value of 6 like the kernel port does. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | |||
| * | Add GPL-2.0+ SPDX-License-Identifier to source files | Wolfgang Denk | 2013-07-24 | -16/+1 |
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> | |||
| * | mips: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment | Anton Staaf | 2011-10-23 | -0/+36 |
| Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Shinya Kuribayashi <skuribay@pobox.com> | ||||
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