summaryrefslogtreecommitdiff
path: root/arch/mips/cpu
Commit message (Collapse)AuthorAgeLines
* MIPS: add possibility to setup initial stack and global data in SRAMDaniel Schwierzeck2016-11-30-0/+7
| | | | | | | | | | This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which a SoC can select if it supports some kind of SRAM. Together with CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be set up in that SRAM. This can be used to provide a C environment also for lowlevel_init(). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: factor out code for initial stack and global dataDaniel Schwierzeck2016-11-30-26/+30
| | | | | | | Move the code for setting up the initial stack and global data to a macro to be able to use it more than once. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: fix iand optimize setup of CP0 registersDaniel Schwierzeck2016-11-30-24/+50
| | | | | | | | | | | | | | Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception. Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too. Initialize cp0 count as early as possible to get the most accurate boot timing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: fix ROM exception vectorsDaniel Schwierzeck2016-11-30-10/+19
| | | | | | | | | | | | When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: make inclusion of ROM exception vectors configurableDaniel Schwierzeck2016-11-30-3/+8
| | | | | | | | | | | | | This adds a compile time option to include code for static exception vectors. Static exception vectors are only needed, when the U-Boot entry point is equal to the CPU reset exception vector address. For instance this is the case when U-Boot is used as ROM in Qemu or booted from parallel NOR flash. When U-Boot is booted from RAM (e.g. loaded there by SPL), the exception vectors need to be setup dynamically, which is done in follow-up commits. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: Hang if run on a secondary CPUPaul Burton2016-09-21-1/+20
| | | | | | | | | | | | | Some systems are configured such that multiple CPUs begin running from their reset vector following a system reset. If this occurs then U-Boot will be run on multiple CPUs simultaneously, which causes all sorts of issues as the multiple instances of U-Boot clobber each other. Prevent this from happening by simply hanging with an infinite loop if we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum as appropriate, is non-zero. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Fix cache maintenance in relocate_code & simplifyPaul Burton2016-09-21-26/+21
| | | | | | | | | | | | | | | | | | | | | The relocate_code function was handling cache maintenance incorrectly. It copied U-Boot to its new location, flushed the caches & then proceeded to apply relocations & jump to the new code without flushing the caches again. This is problematic as the instruction cache could potentially have already fetched instructions that hadn't had relocs applied. Rework this to perform the flush_cache call using the code in the original copy of U-Boot, after having applied relocations to the new copy of U-Boot. The new U-Boot can then be jumped to safely once that cache flush has been performed. As part of this, since the old U-Boot is used up until after that cache flush, complexity around loading values from the GOT using a jump & link instruction & loads from a table is removed. Instead we can simply load the needed values with PTR_LA fromt the original GOT. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Ensure Config.K0=2 applies before any memory accessesPaul Burton2016-09-21-0/+1
| | | | | | | | | | | | During boot we set Config.K0=2 (uncached) such that any accesses to the kseg0 memory region are performed uncached before the caches are initialised. This write to the Config register introduces an execution hazard between it & any following memory accesses (such as the load of _gp), which we need to clear in order to ensure those memory accesses are actually performed uncached. Clear this execution hazard with the insertion of an ehb execution hazard barrier instruction. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Map CM Global Control RegistersPaul Burton2016-09-21-0/+53
| | | | | | | Map the Global Control Registers (GCRs) provided by the MIPS Coherence Manager (CM) in preparation for using some of them in later patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: If we don't need DDR for cache init, init cache firstPaul Burton2016-09-21-0/+9
| | | | | | | | | | On systems where cache initialisation doesn't require zeroed memory (ie. systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined) perform cache initialisation prior to lowlevel_init & DDR initialisation. This allows for DDR initialisation code to run cached & thus significantly faster. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Preserve Config implementation-defined bitsPaul Burton2016-09-21-2/+3
| | | | | | | | | | The coprocessor 0 Config register includes 9 implementation defined bits, which in some processors do things like enable write combining or other functionality. We ought not to wipe them to 0 during boot. Rather than doing so, preserve their value & only clear the bits standardised by the MIPS architecture. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Enable use of the instruction cache earlierPaul Burton2016-09-21-8/+0
| | | | | | | | | Enable use of the instruction cache immediately after it has been initialised. This will only take effect if U-Boot was linked to run from kseg0 rather than kseg1, but when this is the case the data cache initialisation code will run cached & thus significantly faster. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: Probe cache line sizes once during bootPaul Burton2016-09-21-0/+7
| | | | | | | | | | | Rather than probing the cache line sizes on every call of any cache maintenance function, probe them once during boot & store the values in the global data structure for later use. This will reduce the overhead of the cache maintenance functions, which isn't a big deal yet but becomes more important once L2 caches which may expose their properties via coprocessor 2 or the CM are supported. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: provide a default u-boot-spl.ldsDaniel Schwierzeck2016-05-31-0/+90
| | | | | | | | | | | | Provide a default linker script for SPL binaries. Start address and size of text section and BSS section are configurable. All sections are arranged in a way that only relevant sections are kept in the code section for maximum size reduction. All other sections are kept but moved outside the code section to help with debugging. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* MIPS: Use unchecked immediate addition/subtractionPaul Burton2016-05-21-10/+12
| | | | | | | | | | | | In MIPS assembly there have historically been 2 variants of immediate addition - the standard "addi" which traps if an overflow occurs, and the unchecked "addiu" which does not trap on overflow. In release 6 of the MIPS architecture the trapping variants of immediate addition & subtraction have been removed. In preparation for supporting MIPSr6, stop using the trapping instructions from assembly & switch to their unchecked variants. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* mips: Fix compiler warning in cpu.cMarek Vasut2016-05-21-1/+0
| | | | | | | | | | | | | | | There really is zero reason for including netdev.h in generic mips CPU code. Removing the netdev.h from cpu.c also fixes the following compiler warning: In file included from arch/mips/cpu/cpu.c:10:0: include/netdev.h:204:41: warning: 'struct eth_device' declared inside parameter list [enabled by default] int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)); ^ include/netdev.h:204:41: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default] Signed-off-by: Marek Vasut <marex@denx.de> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Use correct spelling of "U-Boot"Bin Meng2016-02-06-1/+1
| | | | | | | | | | Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* MIPS: start.S: fix and optimize instructionsDaniel Schwierzeck2016-02-01-11/+11
| | | | | | | | Fix 32 vs 64 bit load/store instructions. Access CP0_WATCHHI as 32 Bit register. Use 64 Bit register access for clearing gd_data and copying U-Boot. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: initialize board_init_f() argument to zero.Purna Chandra Mandal2016-02-01-1/+1
| | | | | | | | | Argument boot_flags of board_init_f() should be set to 0 as $a0 may be utilized in lowlevel_init() or mips_cache_reset() or previous stage boot-loader. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: fix annotation of _start and relocate_codeDaniel Schwierzeck2016-01-16-7/+5
| | | | | | | Correctly annotate _start and relocate_code as functions to produce more readable disassembly code generated by objdump. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: unify CPU code in arch/mips/cpu/Daniel Schwierzeck2015-01-30-385/+11
| | | | | | | | | Unify and move code in arch/mips/cpu/mips[32|64]/ to arch/mips/cpu/. The CPU specific config.mk files need to remain until CONFIG_STANDALONE_LOAD_ADDR is converted to a global Kconfig symbol. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: move au1x00 SoC code to arch/mips/mach-au1x00Daniel Schwierzeck2015-01-30-2493/+0
| | | | | | | | | | Move all au1x00 code out of arch/mips/cpu/mips32 to allow unification of CPU code in a later patch. The reorganization of the SoC specific header files will be done in a later patch series. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
* MIPS: handle mips64 ST0_KX bit in mips32 start.SPaul Burton2015-01-30-1/+3
| | | | | | | | | In preparation for sharing a single copy of start.S between mips32 & mips64, handle setting the KX bit of the cop0 Status register when the mips32 start.S is built for mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: handle mips64 relocs in mips32 start.SPaul Burton2015-01-30-2/+17
| | | | | | | | | In preparation for sharing a single copy of start.S between mips32 & mips64, handle mips64 relocations in the mips32 start.S when built for mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: use asm.h macros in mips32 start.SPaul Burton2015-01-30-55/+61
| | | | | | | | | | | | | | Where the mips32 & mips64 implementations of start.S differ in terms of access sizes & offsets, use the appropriate macros from asm.h to abstract those differences away. This is in preparation for sharing a single copy of start.S between mips32 & mips64. The exception to this is loads of immediates to be written to the cop0 Config register, which is a 32bit register on mips64 and therefore constants written to it can be loaded as such. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: unify cache initialization codePaul Burton2015-01-29-489/+2
| | | | | | | | | | | | | | The mips32 & mips64 cache initialization code differs only in that the mips32 code supports reading the cache size from coprocessor 0 registers at runtime. Move the more developed mips32 version to a common arch/mips/lib/cache_init.S & remove the now-redundant mips64 version in order to reduce duplication. The temporary registers used are shuffled slightly in order to work for both mips32 & mips64 builds. The RA register is defined differently to suit mips32 & mips64, but will be removed by a later commit in the series after further cleanup. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: unify cache maintenance functionsPaul Burton2015-01-29-167/+0
| | | | | | | | | Move the more developed mips32 version of the cache maintenance functions to a common arch/mips/lib/cache.c, in order to reduce duplication between mips32 & mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: avoid .set ISA for cache operationsPaul Burton2015-01-29-38/+20
| | | | | | | | | | | | As a step towards unifying the cache maintenance code for mips32 & mips64 CPUs, stop using ".set <ISA>" directives in the more developed mips32 version of the code. Instead, when present make use of the GCC builtin for emitting a cache instruction. When not present, simply don't bother with the .set directives since U-boot always builds with -march=mips32 or higher anyway. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: add support for pre-relocation mallocDaniel Schwierzeck2015-01-21-2/+46
| | | | | | | | | | | Implement MIPS specific setup of the gd_t structure to support pre-relocation malloc. If CONFIG_SYS_MALLOC_F_LEN is specified, a memory area will be reserved after the initial stack area and the gd->malloc_base pointer will be initialized. After this patch the new driver model can be used on MIPS. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: add support for CONFIG_SYS_INIT_SP_ADDRDaniel Schwierzeck2015-01-21-2/+12
| | | | | | | | Support the existing config option CONFIG_SYS_INIT_SP_ADDR on MIPS. This allows to move the initial stack to other places than the beginning of RAM. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: use common code from lib/time.cThomas Langer2015-01-21-110/+8
| | | | | | | | | | | | | The common code just needs the C0_COUNT as free running counter, without the need of writing and checking C0_COMPARE. The function get_tbclk() is still implemented here instead of changing all places of CONFIG_SYS_MIPS_TIMER_FREQ to CONFIG_SYS_TIMER_RATE. The change was tested on a MIPS32 system, but as the MIPS64 code was/is the same, this should be no problem. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
* MIPS: fix setup of initial stack frameDaniel Schwierzeck2014-11-27-4/+10
| | | | | | | | | To get correct stack walking and backtrace functionality in gdb, registers fp and ra should be initialized before calling board_init_f or board_init_r. Thus allocating stack space and zeroing it as it is currently done in board.c becomes obsolete. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* kbuild: use SoC-specific CONFIG to descend into SoC directoryMasahiro Yamada2014-11-23-1/+1
| | | | | | Use "obj-$(CONFIG_FOO) += foo/" where it is possible. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* kbuild: Descend into SOC directory from CPU directoryMasahiro Yamada2014-11-23-0/+2
| | | | | | | | | Some CPUs of some architectures have SOC directories. At present, the build system directly descends into SOC directories from the top Makefile, but it should generally descend into each directory from its parent directory. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* include: move various macros to include/linux/kernel.hMasahiro Yamada2014-11-20-2/+0
| | | | | | | | | | | | | | | | | | | | | | | U-Boot has imported various utility macros from Linux scattering them to various places without consistency. In include/common.h are min, max, min3, max3, ARRAY_SIZE, ALIGN, container_of, DIV_ROUND_UP, etc. In include/linux/compat.h are min_t, max_t, round_up, round_down, etc. We also have duplicated defines of min_t in some *.c files. Moreover, we are suffering from too cluttered include/common.h. This commit moves various macros that originate in include/linux/kernel.h of Linux to their original position. Note: This commit simply moves the macros; the macros roundup, min, max, min2, max3, ARRAY_SIZE are different from those of Linux at this point. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* MIPS: add .padding section to linker scriptDaniel Schwierzeck2014-11-01-0/+18
| | | | | | | | | | | | | | | | | | | | | | | Commit 79fd7e649e287228a1445820a72f7dd33baedb96 MIPS: always keep all sections in u-boot ELF binary. Always keep all sections in u-boot ELF binary. Move all unneeded sections after _end to avoid allocating space in the final binary. Also remove .deadcode section which is now obsolete. removed section .deadcode because the original symptoms were not visible anymore. Unfortuneatly the binutils bug still exists. The size of .rel.dyn section is often bigger than needed for all entries. But objcopy only allocates space as much as required for all reloc entries. Thus there is a gap between the last entry and __rel_dyn_end in u-boot.bin. If u-boot is booted from RAM (e.g. in SPL scenarios) that area could contain garbage data which could lead to CPU exceptions during relocation. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: refactor setting of compiler optionsDaniel Schwierzeck2014-11-01-28/+0
| | | | | | | Refactor and unify all compiler settings in arch/mips/config.mk. Also add tune flags for each supported CPU type. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: drop incaip boardDaniel Schwierzeck2014-04-20-649/+0
| | | | | | | | | This is dead hardware and no one is interested in making the necessary changes for upcoming features like generic board or driver model. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wolfgang Denk <wd@denx.de>
* MIPS: define __init_end in u-boot.ldsPaul Burton2014-04-20-0/+1
| | | | | | | | | The generic board code uses the __init_end symbol to calculate monitor_flash_len. Define said symbol for MIPS, equivalent to __image_copy_end which is used for the same purpose in arch/mips/lib/board.c. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MIPS: stub interrupt_init functionPaul Burton2014-04-20-0/+10
| | | | | | | interrupt_init is called unconditionally by the generic board code. Define a stub for it on MIPS like the enable & disable functions. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* mips: xburst: remove remainders of dead boardMasahiro Yamada2014-04-20-842/+0
| | | | | | | | | | Commit 54e458de deleted qi_lb60 board support because of the incompatible license issue. There is no board with XBurst CPU. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: always keep all sections in u-boot ELF binary.Daniel Schwierzeck2014-04-20-26/+30
| | | | | | | | Always keep all sections in u-boot ELF binary. Move all unneeded sections after _end to avoid allocating space in the final binary. Also remove .deadcode section which is now obsolete. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* usb: create common header virtual root hub descriptorsStephen Warren2014-03-10-98/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many USB host controller drivers contain almost identical copies of the same virtual root hub descriptors. Put these into a common file to avoid duplication. Note that there were some very minor differences between the descriptors in the various files, such as: - USB 1.0 vs. USB 1.1 - Manufacturer/Device ID - Max packet size - String content I assume these aren't relevant. Cc: Thomas Lange <thomas@corelatus.se> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Eric Millbrandt <emillbrandt@coldhaus.com> Cc: Pierre Aubert <p.aubert@staubli.com> Cc: Stefan Roese <sr@denx.de> Cc: Daniel Hellstrom <daniel@gaisler.com> Cc: Denis Peter <d.peter@mpl.ch> Cc: Rodolfo Giometti <giometti@linux.it> Cc: Zhang Wei <wei.zhang@freescale.com> Cc: Mateusz Zalega <m.zalega@samsung.com> Cc: Remy Bohmer <linux@bohmer.net> Cc: Markus Klotzbuecher <mk@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Gary Jennejohn <garyj@denx.de> Cc: C Nauman <cnauman@diagraph.com> Cc: David Müller <d.mueller@elsoft.ch> Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Thomas Abraham <t-abraham@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Andrew Murray <amurray@embedded-bits.co.uk> Cc: Matej Frančeškin <matej.franceskin@comtrade.com> Cc: Cliff Cai <cliff.cai@analog.com> Cc: Bryan Wu <cooloney@gmail.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* mips: move CONFIG_MIPS{32, 64} definition to config.mkMasahiro Yamada2014-03-07-6/+2
| | | | | | | | | | | | | | All mips32 boards define CONFIG_MIPS32 in config headers except malta boards which define it in boards.cfg. We can consolidate them by defining it in arch/mips/cpu/mips32/config.mk. CONFIG_MIPS64 definition can be moved to arch/mips/cpu/mips64/config.mk as well. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* config.mk: specify the exact path to standalone linker scriptMasahiro Yamada2014-03-07-3/+6
| | | | | | | | | | | We want to change the build system to include config.mk only from ./Makefile and spl/Makefile. We must prepare for that in this commit. $(src) is a moving target and not handy for our purpose. We must replace it with a fixed path. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* kbuild: change out-of-tree buildMasahiro Yamada2014-02-19-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit changes the working directory where the build process occurs. Before this commit, build process occurred under the source tree for both in-tree and out-of-tree build. That's why we needed to add $(obj) prefix to all generated files in makefiles like follows: $(obj)u-boot.bin: $(obj)u-boot Here, $(obj) is empty for in-tree build, whereas it points to the output directory for out-of-tree build. And our old build system changes the current working directory with "make -C <sub-dir>" syntax when descending into the sub-directories. On the other hand, Kbuild uses a different idea to handle out-of-tree build and directory descending. The build process of Kbuild always occurs under the output tree. When "O=dir/to/store/output/files" is given, the build system changes the current working directory to that directory and restarts the make. Kbuild uses "make -f $(srctree)/scripts/Makefile.build obj=<sub-dir>" syntax for descending into sub-directories. (We can write it like "make $(obj)=<sub-dir>" with a shorthand.) This means the current working directory is always the top of the output directory. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Gerhard Sittig <gsi@denx.de>
* qemu-malta: rename to just "malta"Paul Burton2013-11-09-1/+1
| | | | | | | | | This is in preparation for adapting this board to function correctly on a physical MIPS Malta board. The board is moved into an "imgtec" vendor directory at the same time in order to ready us for any other boards supported by Imagination in the future. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* mips32: detect L1 cache sizes if they're not definedPaul Burton2013-11-09-19/+144
| | | | | | | | | | | | | | | | For boards such as the MIPS Malta with an FPGA core card it is desirable to be able to detect the L1 cache sizes at runtime, since they are not dependant upon the board but on the FPGA bitstream in use. This patch performs that detection when the CONFIG_SYS_[DI]CACHE_SIZE macros are not defined by the board configuration. In cases where the sizes are detected this patch also removes the restriction that the I-cache & D-cache line sizes must be the same, as this is not necessarily true. If the cache sizes are defined by a configuration then they will be hardcoded as before, so this patch will not add overhead to such boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* mips: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-119/+11
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* usb: add enum usb_init_type parameter to usb_lowlevel_initTroy Kisky2013-10-20-1/+1
| | | | | | This parameter will later be used to verify OTG ports. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
generated by cgit v1.1 at 2024-11-09 14:33:25 +0000