Commit message (Expand) | Author | Age | Lines | |
---|---|---|---|---|
* | mips32: detect L1 cache sizes if they're not defined | Paul Burton | 2013-11-09 | -13/+77 |
* | MIPS: mips32/cache.S: use v1 register for indirect function calls | Gabor Juhos | 2013-07-24 | -4/+4 |
* | MIPS: mips32/cache.S: store cache line size in t8 register | Gabor Juhos | 2013-07-24 | -3/+3 |
* | MIPS: mips32/cache.S: save return address in t9 register | Gabor Juhos | 2013-07-24 | -1/+1 |
* | MIPS: mips32/cache.S: remove superfluous register assignment | Gabor Juhos | 2013-07-24 | -2/+1 |
* | Add GPL-2.0+ SPDX-License-Identifier to source files | Wolfgang Denk | 2013-07-24 | -17/+1 |
* | MIPS: don't use camel-case style | Zhi-zhou Zhang | 2012-10-16 | -5/+5 |
* | MIPS: fix inconsistency in config option for cache operation mode | Daniel Schwierzeck | 2012-04-02 | -1/+5 |
* | MIPS: Coding style cleanups on common assembly files | Shinya Kuribayashi | 2011-05-07 | -43/+38 |
* | MIPS: Remove mips_cache_lock() feature | Shinya Kuribayashi | 2011-05-07 | -93/+0 |
* | MIPS: Move content of arch/mips/cpu to arch/mips/cpu/mips32 | Daniel Schwierzeck | 2011-04-02 | -0/+328 |