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* | | | Merge git://git.denx.de/u-boot-dmTom Rini2014-11-24-2/+46
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/serial/serial-uclass.c Signed-off-by: Tom Rini <trini@ti.com>
| * | | | dm: arm: spl: Make driver model linker lists availableSimon Glass2014-11-21-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The linker lists feature is useful in SPL as it holds the driver model platform data. So don't throw away the lists. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
| * | | | dm: arm: spl: Allow simple malloc() in SPLSimon Glass2014-11-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For SPL it is sometimes useful to have a simple malloc() just to permit driver model to work, in the cases where the full malloc() is not made available by the board config. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | dm: at91: Add driver model support for the serial driverSimon Glass2014-11-21-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver model support while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | dm: at91: Add platform data for GPIO on at91sam9260-based boardsSimon Glass2014-11-21-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These boards all have the same GPIO arrangement, so add some common platform data that can be used by all boards. Remove the configs which are no longer required. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | dm: at91: Add driver model support for atmel GPIO driverSimon Glass2014-11-21-0/+6
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | Modify this driver to support driver model, with platform data required to determine the GPIOs that it controls. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | tegra: do not descend into empty directoriesMasahiro Yamada2014-11-23-54/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some tegra makefiles only contain a dummy line to generate a built-in.o. Let's do not descend into such directories. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | kbuild: use SoC-specific CONFIG to descend into SoC directoryMasahiro Yamada2014-11-23-8/+56
| | | | | | | | | | | | | | | | | | | | | | | | Use "obj-$(CONFIG_FOO) += foo/" where it is possible. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | kbuild: Descend into SOC directory from CPU directoryMasahiro Yamada2014-11-23-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some CPUs of some architectures have SOC directories. At present, the build system directly descends into SOC directories from the top Makefile, but it should generally descend into each directory from its parent directory. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | ARM: bcm: Enable five Cygnus boardsSteve Rae2014-11-23-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bcm911360_entphn bcm911360_entphn-ns bcm911360k bcm958300k-ns bcm958305k - updates to support Cygnus and NSP board families better - add functions so CONFIG_ARMV7_NONSEC can be enabled on Cygnus boards Signed-off-by: Steve Rae <srae@broadcom.com>
* | | | linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada2014-11-23-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
* | | | include: move various macros to include/linux/kernel.hMasahiro Yamada2014-11-20-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot has imported various utility macros from Linux scattering them to various places without consistency. In include/common.h are min, max, min3, max3, ARRAY_SIZE, ALIGN, container_of, DIV_ROUND_UP, etc. In include/linux/compat.h are min_t, max_t, round_up, round_down, etc. We also have duplicated defines of min_t in some *.c files. Moreover, we are suffering from too cluttered include/common.h. This commit moves various macros that originate in include/linux/kernel.h of Linux to their original position. Note: This commit simply moves the macros; the macros roundup, min, max, min2, max3, ARRAY_SIZE are different from those of Linux at this point. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | replace DIV_ROUND with DIV_ROUND_CLOSESTMasahiro Yamada2014-11-20-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux-compatible macro DIV_ROUND_CLOSEST is a bit more flexible and safer than DIV_ROUND. For example, foo = DIV_ROUND_CLOSEST(x, y++) works expectedly, but foo = DIV_ROUND(x, y++) does not. (y is incremented twice.) Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | ARM: remove CONFIG_ARM1136 definesMasahiro Yamada2014-11-20-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_CPU_ARM1136 was introduced into Kconfig by commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs). This commit removes all the defines of CONFIG_ARM1136 and replaces the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM1136. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | ARM: remove CONFIG_ARM926EJS definesMasahiro Yamada2014-11-20-12/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_CPU_ARM926EJS was introduced into Kconfig by commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs). This commit removes all the defines of CONFIG_ARM926EJS and replaces the only reference in arch/arm/lib/cache.c with CONFIG_CPU_ARM926EJS. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | ARM: remove CONFIG_ARM920T definesMasahiro Yamada2014-11-20-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_CPU_ARM920T was introduced into Kconfig by commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs). This commit removes all the defines of CONFIG_ARM920T and replaces the only reference in drivers/usb/host/ohci-hcd.c with CONFIG_CPU_ARM920T. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | ARM: remove CONFIG_ARMV7 definesMasahiro Yamada2014-11-20-1/+0
|/ / / | | | | | | | | | | | | | | | | | | | | | Some (not all) of ARMv7 boards define CONFIG_ARMV7, which is useless. Besides, it is never referenced. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | ARM: atmel: add sama5d4 xplained ultra board supportBo Shen2014-11-17-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code for this board supports following features: - Boot media support: NAND flash/SD card/SPI flash - Support LCD display (optional, disabled by default) - Support ethernet - Support USB mass storage Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | ARM: atmel: add sama5d4ek board supportBo Shen2014-11-17-9/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code for this board supports following features: - Boot media support: NAND flash/SD card/SPI flash - Support LCD display - Support ethernet - Support USB mass storage Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm, spl, at91: add spl support for the corvus boardHeiko Schocher2014-11-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | replaces the at91bootstrap code with SPL code. make the spl image with: ./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin this writes the length of the spl image into the 6th execption vector. This is needed from the ROM bootloader. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm, at91, spl: add spl support for the taurus boardHeiko Schocher2014-11-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | replaces the at91bootstrap code with SPL code. make the spl image with: ./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin this writes the length of the spl image into the 6th execption vector. This is needed from the ROM bootloader. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm, spl, at91: add at91sam9260 and at91sam9g45 spl supportHeiko Schocher2014-11-17-97/+430
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add support for using spl code on at91sam9260 and at91sam9g45 based boards. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [adopt Bo's change in spl.c] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm, at91: add missing ddr2 cr register MPDDRC_CR_EBISHARE defineHeiko Schocher2014-11-17-0/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm, at91: compile mpddrc ram init code also for AT91SAM9M10G45Heiko Schocher2014-11-17-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - compile mpddrc ram init code also for AT91SAM9M10G45 based boards. - in CONFIG_SAMA5D3 case, look for the ATMEL_MPDDRC_CR_DECOD_INTERLEAVED in the cr configuration Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm, at91, mpddrc: fix typo in ddr2_init()Heiko Schocher2014-11-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | use the configure value for computing the ba_off value not the value from the cr register. This leaded in a wrong ram configuration on the upcoming corvus spl board support. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm, at91: generate boot.bin file for all atmel SoCHeiko Schocher2014-11-17-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | generate the boot.bin file for all atmel SoC (arm920, arm926, armv7) Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> [fix subject] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | ARM: atmel: spl: make css field configurableBo Shen2014-11-17-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The clock source for master clock can be slow clock, main clock, plla clock or upll clock. So, make the clock source selection field in mckr can be configured. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | ARM: atmel: spl: make initialization more stableBo Shen2014-11-17-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | We need to make sure the main clock ready field in MCFR is set after switch to main crystal oscillator. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2014-11-17-1/+2464
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| * | arm: rmobile: Move rcar-i2c of the address defined to common headerNobuhiro Iwamatsu2014-11-10-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | R-Car SoCs of rmobile have same IP of rcar-i2c, and have same address. This moves rcar-i2c of the address defined to rcar-base.h as common header of R-Car SoCs. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: Move sh-i2c of the address defined to common headerNobuhiro Iwamatsu2014-11-10-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | R-Car SoCs of rmobile have same IP of sh-i2c, and have same address. This moves sh-i2c of the address defined to rcar-base.h as common header of R-Car SoCs, and headers of each SoCs. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: Add support gose boardNobuhiro Iwamatsu2014-11-10-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gose board has R8A7793, 1GB DDR3-SDRAM, USB, Ethernet, and more. This patch supports the following functions: - DDR3-SDRAM - SCIF - QSPI - SPI Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> CC: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: Add support R8A7793Nobuhiro Iwamatsu2014-11-10-1/+2431
| | | | | | | | | | | | | | | | | | | | | | | | Renesas R8A7793 is CPU with Cortex-A15. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-14-5/+15
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| * | arm: mx6: add support for TBS2910 Matrix ARM miniPCSoeren Moch2014-11-13-0/+4
| | | | | | | | | | | | | | | | | | | | | Add initial support for TBS2910 Matrix ARM miniPC. Support includes MMC, Ethernet, UARTs, HDMI, USB, SATA, PCI, I2C, RTC. Signed-off-by: Soeren Moch <smoch@web.de>
| * | mx6: video_skip: Fix crash on NULL pointerNikolay Dimitrov2014-11-13-1/+5
| | | | | | | | | | | | | | | Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Stefano Babic <sbabic@denx.de>
| * | kconfig: imx6: add SUPPORT_SPLJohn Tobias2014-11-13-0/+1
| | | | | | | | | | | | | | | | | | | | | add SUPPORT_SPL feature for iMX6 SabreSD. It need to use mx6sabresd_spl_defconfig to compile it. Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
| * | arm: imx: make bmode command work with SPL/U-Boot comboNikita Kiryanov2014-11-12-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bmode command forces the SoC to use a specific boot device by writing its boot mode into SRC_GPR9, and notifying the SoC of the change using SRC_GPR10[28] bit: if the bit is on, bootROM uses the value in SRC_GPR9 instead of SRC_SMBR1 to determine the boot device. SPL on the other hand is oblivious to this distinction, so once the bootROM loads SPL from the device configured in SRC_GPR10, SPL will attempt to load U-Boot from the device configured in SRC_SMBR1, which is not updated by the bootROM to the value in SRC_GPR9. The result is that the selected boot device is not used across all the boot stages. Update spl_boot_device() to look at gpr9 when necessary. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Heiko Schocher <hs@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2014-11-13-175/+1455
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| * | | sun6i: ehci: Add sun6i ehci supportHans de Goede2014-11-13-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the 2 ehci controllers found on the sun6i (A31) soc. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Marek Vasut <marex@denx.de>
| * | | sun6i: Poke magic sram controller register to avoid cache issuesHans de Goede2014-11-13-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this the cache will only work in write-through mode, and as soon as it is put in write-back mode things break. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sun6i: Add dram initialization codeHans de Goede2014-11-13-3/+804
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add full support for dram initialization, using a fixed clock and autodetection of the memory organization (numbers of channels, bus-width, etc.). This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK, extended with extra initialization sequences and the autodetect algorithm from boot0. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sun4i: Rename dram files to dram_sun4i.xHans de Goede2014-11-13-168/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for adding sun6i dram support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sun6i: Add cpucfg register definitionsHans de Goede2014-11-13-3/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Not used atm, for future use (e.g. PSCI). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sun6i: Add clock functions needed for SPL / DRAM initHans de Goede2014-11-13-1/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock_init_safe and clockset_pll5 functions, as these are needed for SPL support resp. DRAM init (which is needed for SPL too). Also add some extra clock register constant defines. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | | sun6i: Add new p2wi controller driverOliver Schinagl2014-11-13-0/+261
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A31 uses a new push-pull two wire interface, which features higher transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8 bytes each time, this driver will only see very little use and thus is limited to single byte transmission only. Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-11-13-143/+11
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| * | | ARM: remove unused CPU directoryMasahiro Yamada2014-11-13-132/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no board with CPU "arm_intcm". Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
| * | | ARM: cache-cp15: Use more accurate typesThierry Reding2014-11-12-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | ARM: cache_v7: Various minor cleanupsThierry Reding2014-11-12-7/+7
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove two gratuituous blank lines, uses u32 (instead of int) as the type for values that will be written to a register, moves the beginning of the variable declaration section to a separate line (rather than the one with the opening brace) and keeps the function signature on a single line where possible. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-19 19:50:44 +0000