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* mmc: exynos_dw_mmc: remove the unused functionJaehoon Chung2016-07-12-1/+0
| | | | | | | | | | This function have maintained for supporting Non-FDT. Now, Almost all SoC are changed to fdt style. So there are no that this function is called anywhere. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: exynos4: dts: add the prefix '/' for aliases nodesJaehoon Chung2016-07-12-10/+10
| | | | | | | It's correct to use '/' as prefix for aliases nodes. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* armv8: Enable CPUECTLR.SMPEN for coherencyMingkai Hu2016-07-08-0/+8
| | | | | | | | | | | | | | | | For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The SMPEN bit should be set before enabling the data cache. If not enabled, the cache is not coherent with other cores and data corruption could occur. For A57/A72, SMPEN bit enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster. This bit should be set before enabling the caches and MMU, or performing any cache and TLB maintenance operations. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* arm: Fix setjmp (again)Alexander Graf2016-07-08-1/+3
| | | | | | | | | | | | Commit e677724 (arm: Fix setjmp) added code to fix compilation of the setjmp code path with thumv1. Unfortunately it missed a constraint that the adr instruction can only refer to 4 byte aligned offsets. So this patch adds the required alignment hooks to make compilation work again even when setjmp doesn't happen to be 4 byte aligned. Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Tom Rini <trini@konsulko.com>
* video: tegra: Move to using simple-panel and pwm-backlightSimon Glass2016-07-05-72/+75
| | | | | | | | | | | | | | | | | | We have standard drivers for panels and backlights which can do most of the work for us. Move the tegra20 LCD driver over to use those instead of custom code. This patch includes device tree changes for the nvidia boards. I have only been able to test seaboard. If this patch is applied, these boards will also need to be synced with the kernel, and updated to use display-timings: - colibri - medcom-wide - paz00 - tec Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: dts: Sync tegra20 device tree files with LinuxSimon Glass2016-07-05-73/+2154
| | | | | | | | Sync everything except the display panel, which will come in a future patch. One USB port is left disabled since we don't want to support it in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* sunxi: Add defconfig and DTS file for Allwinner R16 EVB (Parrot)Quentin Schulz2016-07-02-1/+350
| | | | | | | | | | | | | | | The Parrot Board is an evaluation board with an Allwinner R16 (assumed to be close to an Allwinner A33), 4GB of eMMC, 512MB of RAM, USB host and OTG, a WiFi/Bluetooth combo chip, a micro SD Card reader, 2 controllable buttons, an LVDS port with separated backlight and capacitive touch panel ports, an audio/microphone jack, a camera CSI port, 2 sets of 22 GPIOs and an accelerometer. The DTS file is identical to the one submitted to the upstream kernel. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add missing boot_media fields in the SPL headerOlliver Schinagl2016-07-02-0/+2
| | | | | | | | | | | Commit b19236fd1 ("sunxi: Increase SPL header size to 64 bytes to avoid code corruption") Added defines for MMC0 and SPI as boot identification. After verifying on an OLinuXino Lime2 with NAND and eMMC, the expected values have been confirmed and added to spl.h Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: uniphier: add external IRQ setup codeMasahiro Yamada2016-07-02-0/+44
| | | | | | | | I will carry this work-around until it is cared in the kernel. This looks up the AIDET node and sets up a register to handle active low interrupt signals. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add AIDET nodesMasahiro Yamada2016-07-02-0/+40
| | | | | | | The AIDET (ARM Interrupt Detector Add-on Circuit) is a kind of syscon block related with the interrupt controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: sync Device Trees with upstream LinuxMasahiro Yamada2016-07-02-138/+99
| | | | | | I periodically sync Device Trees for better maintainability. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix typo "talbe"Masahiro Yamada2016-06-30-1/+1
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-06-28-124/+21
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| * armv8: dts: fsl: Remove cpu nodes from Layerscape DTSIsAbhimanyu Saini2016-06-28-105/+0
| | | | | | | | | | | | | | | | | | | | | | | | Currently layescape SoCs are not using cpu nodes. So removing them in favour of compatibly with similar SoCs that have different cores like LS2080A and LS2088A. This has been tested on LS2080AQDS, LS1043ARDB, LS1012ARDB. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCsPrabhakar Kushwaha2016-06-28-16/+16
| | | | | | | | | | | | | | | | | | | | | | Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs. like LS2080A, LS1043A, LS1012A. So append "A" to SoC names. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl_lsch2: Correct the cores frequency initializationHou Zhiqiang2016-06-24-3/+5
| | | | | | | | | | | | | | | | The register CLKCNCSR controls the frequency of all cores in the same cluster. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm: at91: taurus/axm: add DM and DTS supportHeiko Schocher2016-06-26-0/+124
| | | | | | | | | | | | | | | | | | | | add DM and DTS support for the at91 based siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [rebased on current ToT] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
* | arm: at91: smartweb: add DM and DTS supportHeiko Schocher2016-06-26-1/+116
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [rebased on current ToT] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
* | arm: at91: dts: Bring in dts files for AT91SAM9G20 and SAM9260Heiko Schocher2016-06-26-0/+3012
| | | | | | | | | | | | | | | | | | Add this files from Linux v4.6-rc5 66b8a424d: [workqueue: fix ghost PENDING flag while doing MQ IO] Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Andreas Bießmann <andreas@biessmann.org>
* | corvus DTS / DM supportHeiko Schocher2016-06-26-1/+115
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [rebase on current ToT, don't delete gurnard DTB creation] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
* | arm: at91: add CONFIG_AT91SAM9M10G45Heiko Schocher2016-06-26-12/+14
| | | | | | | | | | | | | | add support for CONFIG_AT91SAM9M10G45. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | ARM: at91: Don't invoke spl_boot_device() twiceMarek Vasut2016-06-26-1/+1
| | | | | | | | | | | | | | | | | | | | Since the spl_boot_mode() is now passed the boot device to boot from, make use of it instead of inquiring for the boot device again. This allows board_boot_order() to function correctly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | common: Pass the boot device into spl_boot_mode()Marek Vasut2016-06-26-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPL code already knows which boot device it calls the spl_boot_mode() on, so pass that information into the function. This allows the code of spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets board_boot_order() correctly alter the behavior of the boot process. The later one is important, since in certain cases, it is desired that spl_boot_device() return value be overriden using board_boot_order(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [add newly introduced zynq variant] Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
* | board/BuR: rename kwb board to brxre1Hannes Schmelzer2016-06-24-3/+3
| | | | | | | | | | | | | | Rename B&R kwb board to brxre1 Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Tom Rini <trini@konsulko.com>
* | board/BuR: rename tseries board to brppt1Hannes Schmelzer2016-06-24-3/+3
| | | | | | | | | | | | | | Rename B&R tseries board to brppt1 Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: bcm235xx: update clock frameworkSteve Rae2016-06-24-5/+5
| | | | | | | | | | | | | | | | The handling of the "usage counter" is incorrect, and the clock should only be disabled when transitioning from 1 to 0. Reported-by: Chris Brand <chris.brand@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* | arm: bcm235xx: fix kps ccuChris Brand2016-06-24-5/+1
| | | | | | | | | | | | | | The Kona Peripheral Slave CCU has 4 policy mask registers, not 8. Signed-off-by: Chris Brand <chris.brand@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* | arm: bcm235xx: implement the boot0 hook codeSteve Rae2016-06-24-0/+15
| | | | | | | | | | | | Choose the Kconfig boot0 hook option and implement the required code. Signed-off-by: Steve Rae <srae@broadcom.com>
* | ARM: armv7: refactor Makefile slightlyMasahiro Yamada2016-06-24-9/+2
| | | | | | | | | | | | Use Kbuild standard style where possible. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: move #ifdef to match the error handling codeMasahiro Yamada2016-06-24-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | Match the #ifdef ... #endif and the code, ret = do_something(); if (ret) return ret; This will make it easier to add more #ifdef'ed code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arm64: optimize smp_kick_all_cpusMasahiro Yamada2016-06-24-3/+1
| | | | | | | | | | | | | | | | gic_kick_secondary_cpus can directly return to the caller of smp_kick_all_cpus. We do not have to use x29 register here. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | board: amlogic: Rename folder for Amlogic boardsCarlo Caione2016-06-24-1/+1
| | | | | | | | | | | | | | | | | | s/hardkernel/amlogic/ to have a single place for all the amlogic-based boards. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Beniamino Galvani <b.galvani@gmail.com>
* | omap3: bugfix in timer on rolloverDaniel Gorsulowski2016-06-24-1/+1
|/ | | | Signed-off-by: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
* Kconfig: Add a new DISTRO_DEFAULTS Kconfig optionHans de Goede2016-06-20-9/+0
| | | | | | | | | | | | | | | | | | | | | | DISTRO_DEFAULTS is intended to mirror / replace include/config_distro_defaults.h. The intend is for boards which include this file to select this from their Kconfig files and when moving setting to Kconfig which are #define-ed in config_distro_defaults.h to select this from DISTRO_DEFAULTS so that boards which have selected DISTRO_DEFAULTS will keep the same configuration as before without needing any defconfig file changes. The initial list of selected things matches all settings recently removed from config_distro_defaults.h because they have been converted to Kconfig, with the exception of CMD_ELF and CMD_NET, which have a default of y, if the default of these ever changes they should be selected by DISTRO_DEFAULTS too. For testing and example purposes this commit also converts ARCH_SUNXI to use DISTRO_DEFAULT instead of selecting everything it needs itself. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add PSCI implementation in CChen-Yu Tsai2016-06-20-504/+341
| | | | | | | | | | | | | | To make the PSCI backend more maintainable and easier to port to newer SoCs, rewrite the current PSCI implementation in C. Some inline assembly bits are required to access coprocessor registers. PSCI stack setup is the only part left completely in assembly. In theory this part could be split out of psci_arch_init into a separate common function, and psci_arch_init could be completely in C. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add base address for GICChen-Yu Tsai2016-06-20-4/+6
| | | | | | | | | Instead of hardcoding the GIC addresses in the PSCI implementation, provide a base address in the cpu header. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add CPUCFG debug lock and sun7i cpu power controlsChen-Yu Tsai2016-06-20-1/+6
| | | | | | | | | | | | CPUCFG has an unlisted debug control register, which is used to disable external debug access. Also, sun7i secondary core power controls are in CPUCFG, as there's no separate PRCM block. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Group cpu core related controls togetherChen-Yu Tsai2016-06-20-24/+16
| | | | | | | | | | | | | Instead of listing individual registers for controls to each processor core, list them as an array of registers. This makes accessing controls by core index easier. Also rename "cpucfg_sun6i.h" (which was unused anyway) to the more generic "cpucfg.h", and add packed attribute to struct sunxi_cpucfg. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add missing linux/types.h header for cpucfg_sun6i.hChen-Yu Tsai2016-06-20-0/+2
| | | | | | | | | cpucfg_sun6i.h includes a register definition for the CPUCFG register block. The types used are u32 and u8, which are defined in linux/types.h. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add packed attribute to struct sunxi_prcm_regChen-Yu Tsai2016-06-20-1/+3
| | | | | | | | | struct sunxi_prcm_reg is a representation of the PRCM registers. Add the packed attribute to prevent the compiler from doing funny things. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Make CPUCFG_BASE macro names the same across familiesChen-Yu Tsai2016-06-20-14/+25
| | | | | | | | | Use SUNXI_CPUCFG_BASE across all families. This makes writing common PSCI code easier. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: allocate extra space for PSCI stack in secure section during link phaseChen-Yu Tsai2016-06-20-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | The PSCI implementation expects at most 2 pages worth of space reserved at the end of the secure section for its stacks. If PSCI is relocated to secure SRAM, then everything is fine. If no secure SRAM is available, and PSCI remains in main memory, the reserved memory space doesn't cover the space used by the stack. If one accesses PSCI after Linux has fully booted, the memory that should have been reserved for the PSCI stacks may have been used by the kernel or userspace, and would be corrupted. Observed after effects include the system hanging or telinit core dumping when trying to reboot. It seems the init process gets hit the most on my test bed. This fix allocates the space used by the PSCI stacks in the secure section by skipping pages in the linker script, but only when there is no secure SRAM, to avoid bloating the binary. This fix is only a stop gap. It would be better to rework the stack allocation mechanism, maybe with proper usage of CONFIG_ macros and an explicit symbol. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: PSCI: export common PSCI function declarations for C codeChen-Yu Tsai2016-06-20-0/+7
| | | | | | | | | | | Some common PSCI functions are written in assembly, but it should be possible to use them from C code. Add function declarations for C code to consume. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: PSCI: save and restore clobbered registers in v7_flush_dcache_allChen-Yu Tsai2016-06-20-0/+2
| | | | | | Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: PSCI: use only r0 and r3 in psci_get_cpu_stack_top()Chen-Yu Tsai2016-06-20-9/+9
| | | | | | | | | | | For psci_get_cpu_stack_top() to be usable in C code, it must adhere to the ARM calling conventions. Since it could be called when the stack is still unavailable, and the entry code to linux also expects r1 and r2 to remain unchanged, stick to r0 and r3. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add defconfig and dts file for inet86dz boardHans de Goede2016-06-20-0/+294
| | | | | | | | | | | | | | | The inet86dz board is a board used in 7" tablets from various oems. These tablets are a23 based 7" tablets featuring a 1024x600 LCD, 512MB RAM, 4G NAND, rtl8188etv usb wifi, gsl1680 touchschreen, micro-sd slot, 3.5mm headphone jack and a micro-usb otg connector which doubles as charging port. The dts file this commit adds is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add defconfig and dts file for Polaroid MID2407PXE03 tabletHans de Goede2016-06-20-0/+303
| | | | | | | | | | | | The Polaroid MID2407PXE03 is an a23 based 7" tablet based on a M86_MB V2.0 PCB, featuring a 800x480 LCD, 512MB RAM, 4G NAND, esp8089 wifi, gsl1680 touchschreen, micro-sd slot, 3.5mm headphone jack and a micro-usb otg connector which doubles as charging port. The dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Select USE_TINY_PRINTFHans de Goede2016-06-20-0/+1
| | | | | | | | This gives us a bit more breathing room wrt our SPL size. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-dmTom Rini2016-06-20-28/+64
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| * clk: convert API to match reset/mailbox styleStephen Warren2016-06-19-28/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
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