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| * | sun6i: Add defconfig and dts file for tablets using the inet-q972 PCBHans de Goede2016-08-26-0/+294
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a defconfig and dts file for tablets using the generic inet-q972 PCB. Tablets with this PCB feature a mini-hdmi output, micro-usb usb-host, micro-usb usb-otg, 3.5mm headphone jack, a micro sd slot, (mini) power-barrel and an usb wifi module. This has been tested on a 9.7" 1024x768 qware qw tb9718-qhd tablet. The dts files are identical to the ones submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | treewide: fix "followings" to "following"Masahiro Yamada2016-08-26-2/+2
| | | | | | | | | | | | Most of them are my mistakes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arm: cache: always flush cache line size for page tableStefan Agner2016-08-26-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* | arm: cache: add support for LPAE for region D$ behaviorStefan Agner2016-08-26-0/+4
| | | | | | | | | | | | | | Add LPAE support for mmu_set_region_dcache_behaviour. The function is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* | arch/arm/Kconfig: Whitespace correctionTom Rini2016-08-26-28/+28
| | | | | | | | | | | | Use a tab not 8 spaces. Signed-off-by: Tom Rini <trini@konsulko.com>
* | ARM: Move SYS_CACHELINE_SIZE over to KconfigTom Rini2016-08-26-46/+32
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr>
* Merge branch 'master' of git://www.denx.de/git/u-boot-marvellTom Rini2016-08-26-21/+31
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| * arm: mvebu: a38x: typo fix cpabilities -> capbilitiesChris Packham2016-08-26-1/+1
| | | | | | | | | | Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: a38x: update serdes error handlingChris Packham2016-08-26-19/+20
| | | | | | | | | | | | | | | | | | Ensure appropriate error messages are generated. Previously all errors indicated that the serdes was already in use. Now appropriate error messages are given. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: Add support for NAND interface on A-38xChris Packham2016-08-26-1/+10
| | | | | | | | | | | | | | | | | | | | | | The NAND interface on the Armada-38x series is similar to that on the Armada-XP. The key difference is that the NAND ECC clock ratio is provided via the DFX Server registers instead of the Core Clock. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | ARM: tegra: remove stale nvidia, bpmp I2C DT propertyStephen Warren2016-08-25-1/+0
| | | | | | | | | | | | | | | | | | | | The nvidia,bpmp property is left over from an old BPMP I2C binding, and shouldn't be present. Remove it from the SoC DT file, and update the I2C driver not to parse it; the value wasn't used for anything any more anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: fix Tegra186 SDHCI clock/reset namesStephen Warren2016-08-25-4/+2
| | | | | | | | | | | | | | | | | | The Tegra SDHCI binding dictates that the reseet name for the Tegra SDHCI clock be "sdhci" not "sdmmc", and that the clock is accessed by index rather than by name. Fix the Tegra186 DT and MMC driver to honor this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: fix Tegra186 I2C clock nameStephen Warren2016-08-25-8/+8
|/ | | | | | | | The Tegra I2C binding dictates that the clock name for the Tegra I2C clock be "div-clk" not "i2c". Fix the Tegra186 DT and I2C driver to honor this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2016-08-20-32/+9120
|\ | | | | | | | | [trini: Drop CMD_BOOTI as it's now on by default on ARM64] Signed-off-by: Tom Rini <trini@konsulko.com>
| * ARM: rmobile: r8a7795: Add MMU layoutNobuhiro Iwamatsu2016-08-17-1/+31
| | | | | | | | | | | | This add MMU layout for R8A7795 of Renesas ARM64 SoC. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: Add BLANCHE board supportmasakazu.mochizuki.wd@hitachi.com2016-08-17-25/+2983
| | | | | | | | | | | | | | | | | | | | BLANCHE is development board based on R-Car V2H SoC (R8A7792) This commit supports the following periherals: - SCIF, Ethernet, QSPI, MMC Signed-off-by: Masakazu Mochizuki <masakazu.mochizuki.wd@hitachi.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Add support salvator-x boardNobuhiro Iwamatsu2016-08-17-0/+16
| | | | | | | | | | | | | | | | Salvator-x is an entry level development board based on R-Car H3 SoC (R8A7795). This commit supports SCIF only. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Add support R8A7795Nobuhiro Iwamatsu2016-08-17-0/+5874
| | | | | | | | | | | | | | | | | | Renesas R8A7795 is CPU with Cortex-a57. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Add support R-Car Generation 3Nobuhiro Iwamatsu2016-08-17-0/+193
| | | | | | | | | | | | | | This adds supporting R-Car Generation 3 (Gen3) as Renesas ARM64 SoC. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Create R-Car 32bit (Gen1 and Gen2) for KconfigNobuhiro Iwamatsu2016-08-17-82/+96
| | | | | | | | | | | | This creates Kconfig of R-Car 32bit for Kconfig of R-Car 64bit (Gen3). Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: Rmobile: Rename CONFIG_RMOBILE to CONFIG_ARCH_RMOBILENobuhiro Iwamatsu2016-08-17-5/+7
| | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Move SoC headers to mach-rmobile/include/machNobuhiro Iwamatsu2016-08-17-0/+0
| | | | | | | | | | | | Move form arch/arm/include/asm/arch-rmobile/ to arch/arm/mach-rmobile/include/mach/. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Move SoC sources to mach-rmobileNobuhiro Iwamatsu2016-08-17-2/+3
| | | | | | | | | | | | Move from arch/arm/cpu/armv7/rmobile/ to arch/arm/mach-rmobile/. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | ARM: OMAP4+: vcores: Remove duplicated codeLokesh Vutla2016-08-20-52/+10
| | | | | | | | | | | | | | | | | | | | There is no reason to duplicate code for DRA7xx platforms as there can be Rail grouping. The maximum voltage detection algorithm can still be run on other platforms with no Rail grouping and does not harm as it gives the same result. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: OMAP5+: vcores: Drop unnecessary #ifndefsLokesh Vutla2016-08-20-6/+3
| | | | | | | | | | | | | | | | | | | | gpio_en field is introduced to detect if pmic is controlled by GPIO. Make this field 0 on all TPS659* pmics available on DRA7/OMAP5 based platforms and remove the #ifndefs. Reviewed-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | cmd: Split 'bootz' and 'booti' out from 'bootm'Tom Rini2016-08-20-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | The bootz and booti commands rely on common functionality that is found in common/bootm.c and common/bootm_os.c. They do not however rely on the rest of cmd/bootm.c to be implemented so split them into their own files. Have various Makefiles include the required infrastructure for CONFIG_CMD_BOOT[IZ] as well as CONFIG_CMD_BOOTM. Move the declaration of 'images' over to common/bootm.c. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* | ARM: dts: k2g-evm: enable mmc/sd suppportSekhar Nori2016-08-16-0/+8
| | | | | | | | | | | | | | | | | | | | | | The K2G EVM from TI has an SD card slot as well as onboard eMMC for data storage. Enable support for these. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: dts: K2G: Add support for MMC controllerSekhar Nori2016-08-16-0/+23
| | | | | | | | | | | | | | | | | | K2G SoC from TI has two MMC/SD controllers. Add device tree data for these. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | vexpress: Check TC2 firmware support before defaulting to nonsec bootingJon Medhurst \(Tixy\)2016-08-15-5/+10
| | | | | | | | | | | | | | | | | | | | The firmware on TC2 needs to be configured appropriately before booting in nonsec mode will work as expected, so test for this and fall back to sec mode if required. Signed-off-by: Jon Medhurst <tixy@linaro.org> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-08-15-3/+1797
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| * | ARM: at91/dt: Add device tree for SAMA5D2 XplainedWenyou Yang2016-08-15-0/+874
| | | | | | | | | | | | | | | | | | Add device tree for SAMA5D2 Xplained board. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | atmel: Bring in at91 pio4 device tree file and bindingsWenyou Yang2016-08-15-0/+880
| | | | | | | | | | | | | | | | | | | | | | | | Bring in required device tree file and bindings from Linux. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | gpio: atmel_pio4: Move PIO4 definitions to head fileWenyou Yang2016-08-15-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | In order to make these PIO4 definitions shared with AT91 PIO4 pinctrl driver, move them from the existing gpio driver to the head file, and rephrase them. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | clk: at91: Add clock driverWenyou Yang2016-08-15-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | ARM: tegra: reduce CSITE clock from 204M to 136MBryan Wu2016-08-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The L4T kernel complains about a CSITE clock rate above 144MHz, presumably because the HW is only characterized for a clock less than that. Adjust the rate to 136MHz to avoid the warning and stay in spec. Signed-off-by: Bryan Wu <pengw@nvidia.com> (swarren, re-wrote commit description) Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | ARM: tegra: move ft_system_setup()Stephen Warren2016-08-15-31/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, ft_system_setup() is implemented by board*.c, which are a bit of a dumping ground for a bunch of unrelated functionality, and separate versions exist for pre-Tegra186 and Tegra186. Move the implementation into a separate file to separate functionality, and allow sharing. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | ARM: tegra: enable PCIe controller on p2771-0000Stephen Warren2016-08-15-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p2771-0000 has a couple of PCIe ports; one physically x4 desktop PCI connector (which may run at x2 electrically, depending on the board version and configuration) and a x1 connection to the M.2 slot (which may not be active, depending on the board version and configuration). This change enables those. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | ARM: tegra: enable SD card on p2771-0000Stephen Warren2016-08-15-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that clock and reset drivers exist for Tegra186, we can enable the SD card controller. Now that a BPMP I2C driver exists for Tegra186, we can communicate with the PMIC to enable power to the SD card. Hook up the DT content and board code required to make the SD card work. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | ARM: tegra: enable I2C buses for P2771-0000Bryan Wu2016-08-15-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable I2C devices in DT and enable building tegra_i2c.c driver. Signed-off-by: Bryan Wu <pengw@nvidia.com> (swarren, commit msg rework, fixed DT node sort order) Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | mmc: tegra: port to standard clock/reset APIsStephen Warren2016-08-15-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra186 supports the new standard clock and reset APIs. Older Tegra SoCs still use custom APIs. Enhance the Tegra MMC driver so that it can operate with either set of APIs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | reset: add Tegra186 reset driverStephen Warren2016-08-15-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Tegra186, on-SoC reset signals are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | clock: add Tegra186 clock driverStephen Warren2016-08-15-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. A tegra/ sub-directory is created to follow the existing pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | misc: add Tegra BPMP driverStephen Warren2016-08-15-0/+1593
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra BPMP (Boot and Power Management Processor) is a separate auxiliary CPU embedded into Tegra to perform power management work, and controls related features such as clocks, resets, power domains, PMIC I2C bus, etc. This driver provides the core low-level communication path by which feature-specific drivers (such as clock) can make requests to the BPMP. This driver is similar to an MFD driver in the Linux kernel. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | kconfig: use bool instead of boolean for type definition attributesMasahiro Yamada2016-08-12-5/+5
| | | | | | | | | | | | | | | | | | | | Linux stopped the use of keyword 'boolean' in Kconfig. Refer to commit 6341e62b212a2541efb0160c470e90bd226d5496 ("kconfig: use bool instead of boolean for type definition attributes") in Linux Kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: dts: dra7xx-evm: add evm_3v3_sd regulatorVignesh R2016-08-12-2/+22
| | | | | | | | | | | | | | | | | | | | Add a node for evm_3v3_sd using onboard PCF GPIO expander which feeds on to mmc vdd. Update mapping for vmmc-supply and vmmc_aux-supply. evm_3v3_sd supplies to SD card vdd, and ldo1 to sdcard i/o lines. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | drivers/sysreset: group sysreset driversMax Filippov2016-08-12-181/+0
| | | | | | | | | | | | | | | | Create drivers/sysreset and move sysreset-uclass and all sysreset drivers there. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | ARM: non-sec: flush code cacheline alignedStefan Agner2016-08-12-1/+3
| | | | | | | | | | | | | | | | | | | | Flush operations need to be cacheline aligned to take effect, make sure to flush always complete cachelines. This avoids messages such as: CACHE: Misaligned operation at range [00900000, 009004d9] Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-08-11-172/+527
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| * | ARM: uniphier: add PSCI support for UniPhier ARMv7 SoCsMasahiro Yamada2016-08-11-2/+269
| | | | | | | | | | | | | | | | | | Currently, only the CPU_ON function is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: add uniphier_cache_set_active_ways()Masahiro Yamada2016-08-11-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | This outer cache allows to control active ways independently for each CPU, so this function will be useful to set up active ways for a specific CPU. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-11-06 13:57:49 +0000