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* lpc32xx: fix calculation of HCLK PLL output clockVladimir Zapolskiy2015-10-11-5/+5
| | | | | | | | Execution branches on feedback mode are swapped, this has no effect if default direct mode is on (then p_div is equal to 1 and Fout equals to Fcco), that's why the problem remained unnoticed for a long time. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* lpc32xx: remove surplus clock cycle in PL175 WAIT_OEN configVladimir Zapolskiy2015-10-11-1/+1
| | | | | | | | | | | | | | According to ARM PrimeCell PL175 documentation WAIT_OEN config value is defined without any additional clocks added to the value set by a client, the change fixes the wrong interface to WAIT_OEN config. The change also touches a single user of LPC32xx EMC and corrects configured "output enable delay" value on its side according to the changed interface. No functional change intended. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* arndale: Apply Cortex-A15 errata #773022 and #774769Ian Campbell2015-10-11-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We run 4 Arndale boards in our automated test framework, they have been running quite happily for quite some time using a Debian Wheezy userspace. However when upgrading to a Debian Jessie we started seeing frequent segmentation faults from gcc when building the kernel, to the extent that it is unable to successfully build the kernel twice in a row, and often fails on the first attempt. Searching around I found https://bugs.launchpad.net/arndale/+bug/1081417 which pointed towards http://www.spinics.net/lists/kvm-arm/msg03723.html and CPU Errata 773022 and 774769. This errata needs to be applied to all processors in an SMP system, meaning that the usual strategy of applying them in arch/arm/cpu/armv7/start.S is not appropriate (since that applies to the boot processor only). Instead we apply these errata in the secure monitor which is code that is traversed by all processors as they are brought up. The net affect on Arndale is that ACTLR changes from 0x40 to 0x2000042. I ran 17 kernel compile iterations overnight with no segfaults. Runtime testing was done on our v2014.10 based branch and forward ported (with only minimal and trivial contextual conflicts) to current master, where it has been build tested only. I suppose in theory these errata apply to any Exynos5250 based boards, but Arndale is the only one I have access to and I have therefore chosen to be conservative and only apply it there. Also, reorder CONFIG_ARM_ERRATA_794072 in README to make the list numerically sorted. Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
* vexpress64: fvp dram: add DRAM configurationRyan Harkin2015-10-11-0/+9
| | | | | | | | | | | | | | | | | | | | Create an additional FVP configuration to boot images pre-loaded into DRAM. Sometimes it's preferential to boot the model by loading the files directly into DRAM via model parameters, rather than using SemiHosting. An example of model parmaters that are used to pre-load the files into DRAM: --data cluster0.cpu0=Image@0x80080000 \ --data cluster0.cpu0=fvp-base-gicv2-psci.dtb@0x83000000 \ --data cluster0.cpu0=uInitrd@0x84000000 Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> [trini: Update board/armltd/vexpress64/Kconfig logic] Signed-off-by: Tom Rini <trini@konsulko.com>
* dm: dts: ls1021a-twr: Enable DSPI2 on LS1021ATWRYuan Yao2015-10-11-0/+16
| | | | | | | | | Erratum A-008022 has been fixed on LS1021A Rev2.0. So we can use DSPI2 now, this patch enable DSPI2 in dts for LS1021ATWR. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* rockchip: Reconfigure the malloc based to point to system memorySjoerd Simons2015-10-03-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | When malloc_base initially gets setup in the SPL it is based on the current (early) stack pointer, which for rockchip is pointing into SRAM. This means simple memory allocations happen in SRAM space, which is somewhat unfortunate. Specifically a bounce buffer for the mmc allocated in SRAM space seems to cause the mmc engine to stall/fail causing timeouts and a failure to load the main u-boot image. To resolve this, reconfigure the malloc_base to start at the relocated stack pointer after DRAM has been setup. For reference, things did work fine on rockchip before 596380db was merged to fix memalign_simple due to a combination of rockchip SDRAM starting at address 0 and the dw_mmc driver not checking errors from bounce_buffer_start. As a result, when a bounce buffer needed to be allocated mem_align simple would fail and return NULL. The mmc driver ignored the error and happily continued with the bounce buffer address being set to 0, which just happened to work fine.. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-fdtTom Rini2015-10-03-6/+8
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| * trats: fdt: disable unused DW MMCPrzemyslaw Marczak2015-10-03-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This device uses SDHCI driver, for eMMC and SD cards. Trying bind the DW MMC driver with fdt node without all required properties, causes printing an error. This commit disables the DW MMC node. Tested-on: Trats Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Łukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
| * mach-exynos: clock: restore calling dead exynos4_get_mmc_clk()Przemyslaw Marczak2015-10-03-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After rework of code by: commit: d952796 Exynos5: Use clock_get_periph_rate generic API function get_mmc_clk() always returns -1 for Exynos 4. This was caused by omitting, that SDHCI driver for Exynos 4, calls get_mmc_clk(), with mmc device number as argument, instead of pinmux peripheral id, like DW MMC driver for Exynos 5. By this commit, the code directly calls a proper function to get mmc clock for Exynos 4, without checking the peripheral id. Tested on: Odroid U3/X2, Trats, Trats2, Odroid XU3, Snow (by Simon). Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | sunxi: Add generic defconfigs for A23 Q8 tablets with 800x480 LCDHans de Goede2015-10-03-1/+67
|/ | | | | | | | | | | | | | | | | | | | | The 7" Q8 tablet enclosure is used for a ton of slightly different cheap chinese tablets. There are some differences in which accelerometer / wifi is used, but other then that these are all the same from a u-boot / kernel pov. When we get to adding accelerometer support the plan is to add some kind of autodetection and mangle the dt accordingly (likely using the new quirks mechanism). For now this is a non issue as we do not yet have accelerometer support, and in the future, some sort of auto-detect is the way to go as we cannot expect users to exactly know what is inside their tablet. The dts files this commit adds are identical to the ones submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-10-02-135/+111
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| * vf610: add support for Phytec PCM052Albert ARIBAUD \(3ADEV\)2015-10-02-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Devices supported are: - NFC (NAND FLASH) - MMC - QSPI (SPI NOR FLASH) - I2C (only bus 2) - I2C RTC - I2C EEPROM - FEC Patch-series: 2 - remove useless CONFIG_SYS_SPD_BUS_NUM from config - remove include of config_cmd_default.h - remove duplicate CONFIG_CMD_NET Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * vf610: refactor DDRMC codeAlbert ARIBAUD \\(3ADEV\\)2015-10-02-135/+104
| | | | | | | | | | | | | | | | The VF610 DDRMC driver code contains settings which are board-specific. Move these out to boards so that new boards can define their own without having to modify the driver. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * imx: mx6: correct enable_fec_anatop_clockPeng Fan2015-10-02-0/+2
| | | | | | | | | | | | | | | | | | We should follow 'read->set/clr bit->write' flow for enable_fec_anatop_clock, otherwise we may overridden configuration before enable_fec_anatop_clock. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Cc: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge git://git.denx.de/u-boot-marvellTom Rini2015-09-30-15/+23
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| * | arm: mvebu: timer.c: Explicitly move "init_done" var to data sectionStefan Roese2015-10-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As reported by Simon Guinot, commit ade741b3 "arm: mvebu: Call timer_init early before PHY and DDR init" breaks Kirkwood platforms. As the static variable "init_done" is not available at that early boot time. This patch moves it to explicitly to the data section, making it available at that time. Signed-off-by: Stefan Roese <sr@denx.de> Reported-by: Simon Guinot <simon.guinot@sequanux.org> Cc: Luka Perkov <luka.perkov@sartura.hr> Tested-by: Simon Guinot <simon.guinot@sequanux.org>
| * | arm: mvebu: Fix internal register config on A38xStefan Roese2015-10-01-14/+22
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently booting on A38x is broken. As the current code tries to detect the SoC family to disable the MMU for the A38x at runtime. But before the internal registers are switched to the new location (0xf100.0000), this runtime detection does not work. As all macros / defines are already assigned to the new location at 0xf100.0000. But the registers are sill mapped to the default location at 0xd000.0000. This patch now makes sure, no such runtime detection is used before the internal registers are configured to the new location. After this, the remaining cache cleanup is executed. Signed-off-by: Stefan Roese <sr@denx.de> Reported-by: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | sunxi: Add generic defconfigs for A33 Q8 tablets with 1024x600 / 800x480 LCDHans de Goede2015-09-29-0/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 7" Q8 tablet enclosure is used for a ton of slightly different cheap chinese tablets. There are some differences in which accelerometer / wifi is used, but other then that these are all the same from a u-boot / kernel pov. When we get to adding accelerometer support the plan is to add some kind of autodetection and mangle the dt accordingly (likely using the new quirks mechanism). For now this is a non issue as we do not yet have accelerometer support, and in the future, some sort of auto-detect is the way to go as we cannot expect users to exactly know what is inside their tablet. The dts[i] files this commit adds are identical to the ones submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: retrieve FEL-provided values to environment variablesBernhard Nortmann2015-09-29-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends the misc_init_r() function on sunxi boards to test for the presence of a suitable "sunxi" SPL header. If found, and the loader ("fel" utility) provided a non-zero value for the boot.scr address, then the corresponding environment variable fel_scriptaddr gets set. misc_init_r() also sets (or clears) the "fel_booted" variable depending on the active boot device, using the same logic as spl_boot_device(). The goal is to provide sufficient information (within the U-Boot environment) to make intelligent decisions on how to continue the boot process, allowing specific customizations for the "FEL boot" case. Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: (mksunxiboot) signature to indicate "sunxi" SPL variantBernhard Nortmann2015-09-29-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch follows up on a discussion of ways to improve support for the sunxi FEL ("USB boot") mechanism, especially with regard to boot scripts, see: https://groups.google.com/d/msg/linux-sunxi/wBEGUoLNRro/rHGq6nSYCQAJ The idea is to convert the (currently unused) "pad" bytes in the SPL header into an area where data can be passed to U-Boot. To do this safely, we have to make sure that we're actually using our "sunxi" flavor of the SPL, and not the Allwinner boot0. The modified mksunxiboot introduces a special signature to the SPL header in place of the "pub_head_size" field. This can be used to reliably distinguish between compatible versions of sunxi SPL and anything else (older variants or Allwinner's boot0). Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: move SPL-related definitions to platform-specific includeBernhard Nortmann2015-09-29-12/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | The sunxi platform currently doesn't seem to make any use of the asm/arch-sunxi/spl.h file. This patch moves some declarations from tools/mksunxiboot.c into it. This enables us to reuse those definitions when extending the sunxi board code (boards/sunxi/boards.c). Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Simplify spl board_init_f functionHans de Goede2015-09-29-5/+0
|/ | | | | | | | crt0.S will both memset the bss sectioan and call board_init_r for us, so there is no need to do either ourselves. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* arm: Drop old non-generic-board codeSimon Glass2015-09-28-709/+0
| | | | | | | This code is no-longer used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Bießmann <andreas.devel@gmail.com>
* arm: Remove wireless_space boardSimon Glass2015-09-28-4/+0
| | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Remove da830evm boardSimon Glass2015-09-28-3/+0
| | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* ARM: hikey: hi6220: Migrate over to DM_SERIAL and use UART3 by default.Peter Griffin2015-09-28-1/+1
| | | | | | | | | | | | | | | | | | | Use DM for the pl01x serial driver on hikey. Also allow UART0 or UART3 to be chosen via Kconfig. By default we now output to UART3 as the latest version of ATF outputs to this UART. Also UART3 comes out on the LS connector, as opposed to UART0 which goes to a unpopulated header. As part of this change we also enable CONFIG_BOARD_EARLY_INIT_F and call the pinmux configuration code for the UART. Before we were relying on ATF having already configured the pin configuration. NB: Upstream Linux kernel doesn't yet support UART3, so serial console will still be output on UART0 when booting a upstream kernel. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: hikey: Select DM, DM_GPIO from KconfigPeter Griffin2015-09-28-0/+2
| | | | | | | | Most platforms enable these options from Kconfig rather than the configs header file. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: hi6220: Add UART0 and UART3 base addressesPeter Griffin2015-09-28-0/+3
| | | | | Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-09-24-10/+6
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| * imx: fix coding stylePeng Fan2015-09-24-3/+2
| | | | | | | | | | | | | | Fix coding style. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx-common: wrap boot_mode_apply with CONFIG_CMD_BMODEPeng Fan2015-09-24-0/+2
| | | | | | | | | | | | | | boot_mode_apply should be applied only with CONFIG_CMD_BMODE enabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx7: discard unused global variablePeng Fan2015-09-24-2/+0
| | | | | | | | | | | | | | Discard unused global variable. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx-common: consider mux_ctrl_ofs when setting mux_modePeng Fan2015-09-24-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some i.MXes use __NA_ or 0 to avoid setting mux_mode, but the following patch only take i.MX6/7 into consideration. "c3c8a5748897b24f18618047804317167a531dd3 imx-common: fix iomux settings" Use is_soc_type(MXC_CPU_MX7) to avoid breaking other i.MXes when setting mux_mode. In this patch, switch to use "asm/imx-common/sys_proto.h" to avoid build break for "is_soc_type" for vf610 and mx25. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
| * imx: mx7: drop select CPU_V7 for board targetPeng Fan2015-09-20-1/+0
| | | | | | | | | | | | | | drop select CPU_V7 for board target, since ARCH_MX7 selects CPU_V7. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx-common: fix iomux settingsPeng Fan2015-09-20-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | When setting iomux for a pin mux, there is no need to check mux_ctrl_ofs. Also If still checking mux_ctrl_ofs, we have no chance to set iomux for i.MX7D IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00, because the mux_ctrl_ofs for this register is 0. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-09-24-2/+2
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| * | arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config filesDinh Nguyen2015-09-23-2/+2
| |/ | | | | | | | | | | | | | | | | Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA board config files. Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* | ARM: dts: uniphier: use SPDX-License-IdentifierMasahiro Yamada2015-09-25-37/+1
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: fix init page table for ProXstream2/PH1-LD6b USB bootMasahiro Yamada2015-09-25-4/+2
| | | | | | | | | | | | | | | | Currently, the USB boot mode is supported by an external loader and U-boot proper image is put on the section 0. This commit allows access there. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: add ProXstream2 and PH1-LD6b supportMasahiro Yamada2015-09-25-1/+695
| | | | | | | | | | | | | | The DDR SDRAM initialization code has not been mainlined yet, but U-Boot proper should work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: add PH1-Pro5 supportMasahiro Yamada2015-09-25-1/+411
| | | | | | | | | | | | | | The DDR SDRAM initialization code has not been mainlined yet, but U-Boot proper should work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: allow to enable multiple SoCsMasahiro Yamada2015-09-25-429/+1068
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, the Kconfig menu in mach-uniphier only allowed us to choose one SoC to be compiled. Each SoC has its own defconfig file for the build-test coverage. Consequently, some defconfig files are duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and CONFIG_{SOC_NAME}=y. Now, most of board-specific parameters have been moved to device trees, so it makes sense to include init code of multiple SoCs into a single image as long as the SoCs have similar architecture. In fact, some SoCs of UniPhier family are very similar: - PH1-LD4 and PH1-sLD8 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit) This commit will be helpful to merge some defconfig files for better maintainability. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: unify low-level debug init codeMasahiro Yamada2015-09-25-152/+115
| | | | | | | | | | | | | | Move init code of low-level debug into a single file. This is helpful to create an image that runs on multiple SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: fix glitch signal problem for low-level debugMasahiro Yamada2015-09-25-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, IECTRL is enabled after pin-mux settings for the low-level debugging for PH1-LD4 and PH1-sLD8. While IECTRL is disabled, input signals are pulled-down, i.e. glitch signal (Low to High transition) problem occurs if pin-mux is set up first. As a result, one invalid character is input to the UART block and the auto-boot counting is terminated immediately. The correct initialization procedure is: [1] Enable IECTRL (if IECTRL exists for the pins) [2] Set up pin-muxing [3] Deassert the reset of the hardware block Currently, the low-level debugging is working for PH1-sLD3 and PH1-Pro4, but just in case, follow the sequence for all the SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: delete unneeded input enable for low-level debugMasahiro Yamada2015-09-25-5/+0
| | | | | | | | | | | | | | The UART I/O ports for PH1-Pro4 has no input enable controlling. This code is useless. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_*Masahiro Yamada2015-09-25-15/+14
| | | | | | | | | | | | | | I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify they belong to UniPhier SoC family. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: allow to disable CONFIG_MICRO_SUPPORT_CARDMasahiro Yamada2015-09-25-0/+4
| | | | | | | | | | | | Without this, build fails if CONFIG_MICRO_SUPPORT_CARD is disabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: move CONFIG_SUPPORT_CARD_* macros to local fileMasahiro Yamada2015-09-25-7/+10
| | | | | | | | | | | | | | It is no longer necessary to define CONFIG_SUPPORT_CARD_* globally. Move them to a C file as local macros. Also, rename the C file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: refactor LED functionMasahiro Yamada2015-09-25-128/+96
| | | | | | | | | | | | | | | | | | | | The macro, led_write(), is now only used in C sources. There is no more reason to keep the tricky assembly macro. Replace it with a new C function led_puts(). Also, rename board.h to micro-support-card.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: remove useless wrapper functionsMasahiro Yamada2015-09-25-17/+10
| | | | | | | | | | | | | | | | | | | | The wrapper functions, uniphier_board_*, are just making function calls complex. Remove them. Also, use empty inline functions in case CONFIG_MICRO_SUPPORT_CARD is disabled, so that prototype checking works. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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